* [Qemu-devel] [PATCH] i386: Introduce ARAT CPU feature @ 2015-05-24 15:16 Jan Kiszka 2015-05-25 13:23 ` Paolo Bonzini 0 siblings, 1 reply; 7+ messages in thread From: Jan Kiszka @ 2015-05-24 15:16 UTC (permalink / raw) To: Eduardo Habkost, Paolo Bonzini; +Cc: qemu-devel, kvm [-- Attachment #1: Type: text/plain, Size: 6194 bytes --] From: Jan Kiszka <jan.kiszka@siemens.com> ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> --- target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- target-i386/cpu.h | 3 +++ target-i386/kvm.c | 2 ++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 3305e09..e435a08 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -284,6 +284,17 @@ static const char *cpuid_xsave_feature_name[] = { NULL, NULL, NULL, NULL, }; +static const char *cpuid_6_feature_name[] = { + NULL, NULL, "arat", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) @@ -339,6 +350,7 @@ static const char *cpuid_xsave_feature_name[] = { CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ #define TCG_APM_FEATURES 0 +#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT typedef struct FeatureWordInfo { @@ -408,6 +420,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_reg = R_EAX, .tcg_features = 0, }, + [FEAT_6_EAX] = { + .feat_names = cpuid_6_feature_name, + .cpuid_eax = 6, .cpuid_reg = R_EAX, + .tcg_features = TCG_6_EAX_FEATURES, + }, }; typedef struct X86RegisterInfo32 { @@ -1001,6 +1018,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, @@ -1030,6 +1049,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E312xx (Sandy Bridge)", }, @@ -1062,6 +1083,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, @@ -1096,6 +1119,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell, no TSX)", }, { @@ -1130,6 +1155,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_RTM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell)", }, @@ -1166,6 +1193,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell, no TSX)", }, @@ -1202,6 +1231,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell)", }, @@ -2358,7 +2389,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 6: /* Thermal and Power Leaf */ - *eax = 0; + *eax = env->features[FEAT_6_EAX]; *ebx = 0; *ecx = 0; *edx = 0; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4ee12ca..800158e 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -412,6 +412,7 @@ typedef enum FeatureWord { FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_SVM, /* CPUID[8000_000A].EDX */ FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ + FEAT_6_EAX, /* CPUID[6].EAX */ FEATURE_WORDS, } FeatureWord; @@ -577,6 +578,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_XSAVE_XGETBV1 (1U << 2) #define CPUID_XSAVE_XSAVES (1U << 3) +#define CPUID_6_EAX_ARAT (1U << 2) + /* CPUID[0x80000007].EDX flags: */ #define CPUID_APM_INVTSC (1U << 8) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index a26d25a..b786359 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -233,6 +233,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, if (!kvm_irqchip_in_kernel()) { ret &= ~CPUID_EXT_X2APIC; } + } else if (function == 6 && reg == R_EAX) { + ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ } else if (function == 0x80000001 && reg == R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH] i386: Introduce ARAT CPU feature 2015-05-24 15:16 [Qemu-devel] [PATCH] i386: Introduce ARAT CPU feature Jan Kiszka @ 2015-05-25 13:23 ` Paolo Bonzini 2015-05-25 14:06 ` [Qemu-devel] [PATCH v2] " Jan Kiszka 0 siblings, 1 reply; 7+ messages in thread From: Paolo Bonzini @ 2015-05-25 13:23 UTC (permalink / raw) To: Jan Kiszka, Eduardo Habkost; +Cc: qemu-devel, kvm On 24/05/2015 17:16, Jan Kiszka wrote: > From: Jan Kiszka <jan.kiszka@siemens.com> > > ARAT signals that the APIC timer does not stop in power saving states. > As our APICs are emulated, it's fine to expose this feature to guests, > at least when asking for KVM host features or with CPU types that > include the flag. The exact model number that introduced the feature is > not known, but reports can be found that it's at least available since > Sandy Bridge. > > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> This looks good, but you need to disable it in older machine types. Paolo > --- > target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- > target-i386/cpu.h | 3 +++ > target-i386/kvm.c | 2 ++ > 3 files changed, 37 insertions(+), 1 deletion(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 3305e09..e435a08 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -284,6 +284,17 @@ static const char *cpuid_xsave_feature_name[] = { > NULL, NULL, NULL, NULL, > }; > > +static const char *cpuid_6_feature_name[] = { > + NULL, NULL, "arat", NULL, > + NULL, NULL, NULL, NULL, > + NULL, NULL, NULL, NULL, > + NULL, NULL, NULL, NULL, > + NULL, NULL, NULL, NULL, > + NULL, NULL, NULL, NULL, > + NULL, NULL, NULL, NULL, > + NULL, NULL, NULL, NULL, > +}; > + > #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) > #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ > CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) > @@ -339,6 +350,7 @@ static const char *cpuid_xsave_feature_name[] = { > CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, > CPUID_7_0_EBX_RDSEED */ > #define TCG_APM_FEATURES 0 > +#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT > > > typedef struct FeatureWordInfo { > @@ -408,6 +420,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > .cpuid_reg = R_EAX, > .tcg_features = 0, > }, > + [FEAT_6_EAX] = { > + .feat_names = cpuid_6_feature_name, > + .cpuid_eax = 6, .cpuid_reg = R_EAX, > + .tcg_features = TCG_6_EAX_FEATURES, > + }, > }; > > typedef struct X86RegisterInfo32 { > @@ -1001,6 +1018,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, > .features[FEAT_8000_0001_ECX] = > CPUID_EXT3_LAHF_LM, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", > }, > @@ -1030,6 +1049,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_EXT3_LAHF_LM, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "Intel Xeon E312xx (Sandy Bridge)", > }, > @@ -1062,6 +1083,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_EXT3_LAHF_LM, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", > }, > @@ -1096,6 +1119,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "Intel Core Processor (Haswell, no TSX)", > }, { > @@ -1130,6 +1155,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_RTM, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "Intel Core Processor (Haswell)", > }, > @@ -1166,6 +1193,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_SMAP, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "Intel Core Processor (Broadwell, no TSX)", > }, > @@ -1202,6 +1231,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_SMAP, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "Intel Core Processor (Broadwell)", > }, > @@ -2358,7 +2389,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > break; > case 6: > /* Thermal and Power Leaf */ > - *eax = 0; > + *eax = env->features[FEAT_6_EAX]; > *ebx = 0; > *ecx = 0; > *edx = 0; > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 4ee12ca..800158e 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -412,6 +412,7 @@ typedef enum FeatureWord { > FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ > FEAT_SVM, /* CPUID[8000_000A].EDX */ > FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ > + FEAT_6_EAX, /* CPUID[6].EAX */ > FEATURE_WORDS, > } FeatureWord; > > @@ -577,6 +578,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_XSAVE_XGETBV1 (1U << 2) > #define CPUID_XSAVE_XSAVES (1U << 3) > > +#define CPUID_6_EAX_ARAT (1U << 2) > + > /* CPUID[0x80000007].EDX flags: */ > #define CPUID_APM_INVTSC (1U << 8) > > diff --git a/target-i386/kvm.c b/target-i386/kvm.c > index a26d25a..b786359 100644 > --- a/target-i386/kvm.c > +++ b/target-i386/kvm.c > @@ -233,6 +233,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, > if (!kvm_irqchip_in_kernel()) { > ret &= ~CPUID_EXT_X2APIC; > } > + } else if (function == 6 && reg == R_EAX) { > + ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ > } else if (function == 0x80000001 && reg == R_EDX) { > /* On Intel, kvm returns cpuid according to the Intel spec, > * so add missing bits according to the AMD spec: > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v2] i386: Introduce ARAT CPU feature 2015-05-25 13:23 ` Paolo Bonzini @ 2015-05-25 14:06 ` Jan Kiszka 2015-05-25 14:16 ` Paolo Bonzini 0 siblings, 1 reply; 7+ messages in thread From: Jan Kiszka @ 2015-05-25 14:06 UTC (permalink / raw) To: Paolo Bonzini, Eduardo Habkost; +Cc: qemu-devel, kvm [-- Attachment #1: Type: text/plain, Size: 7317 bytes --] From: Jan Kiszka <jan.kiszka@siemens.com> ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> --- Changes in v2: - remove feature from Intel CPU types in compat machines hw/i386/pc_piix.c | 10 ++++++++++ target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- target-i386/cpu.h | 3 +++ target-i386/kvm.c | 2 ++ 4 files changed, 47 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 212e263..83133fa 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -312,6 +312,16 @@ static void pc_init_pci(MachineState *machine) static void pc_compat_2_3(MachineState *machine) { + x86_cpu_compat_set_features("Westmere", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("SandyBridge", FEAT_6_EAX, 0, + CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("IvyBridge", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("Haswell-noTSX", FEAT_6_EAX, 0, + CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("Haswell", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("Broadwell-noTSC", FEAT_6_EAX, 0, + CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("Broadwell", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); } static void pc_compat_2_2(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 3305e09..e435a08 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -284,6 +284,17 @@ static const char *cpuid_xsave_feature_name[] = { NULL, NULL, NULL, NULL, }; +static const char *cpuid_6_feature_name[] = { + NULL, NULL, "arat", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) @@ -339,6 +350,7 @@ static const char *cpuid_xsave_feature_name[] = { CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ #define TCG_APM_FEATURES 0 +#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT typedef struct FeatureWordInfo { @@ -408,6 +420,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_reg = R_EAX, .tcg_features = 0, }, + [FEAT_6_EAX] = { + .feat_names = cpuid_6_feature_name, + .cpuid_eax = 6, .cpuid_reg = R_EAX, + .tcg_features = TCG_6_EAX_FEATURES, + }, }; typedef struct X86RegisterInfo32 { @@ -1001,6 +1018,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, @@ -1030,6 +1049,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E312xx (Sandy Bridge)", }, @@ -1062,6 +1083,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, @@ -1096,6 +1119,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell, no TSX)", }, { @@ -1130,6 +1155,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_RTM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell)", }, @@ -1166,6 +1193,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell, no TSX)", }, @@ -1202,6 +1231,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell)", }, @@ -2358,7 +2389,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 6: /* Thermal and Power Leaf */ - *eax = 0; + *eax = env->features[FEAT_6_EAX]; *ebx = 0; *ecx = 0; *edx = 0; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4ee12ca..800158e 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -412,6 +412,7 @@ typedef enum FeatureWord { FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_SVM, /* CPUID[8000_000A].EDX */ FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ + FEAT_6_EAX, /* CPUID[6].EAX */ FEATURE_WORDS, } FeatureWord; @@ -577,6 +578,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_XSAVE_XGETBV1 (1U << 2) #define CPUID_XSAVE_XSAVES (1U << 3) +#define CPUID_6_EAX_ARAT (1U << 2) + /* CPUID[0x80000007].EDX flags: */ #define CPUID_APM_INVTSC (1U << 8) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index a26d25a..b786359 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -233,6 +233,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, if (!kvm_irqchip_in_kernel()) { ret &= ~CPUID_EXT_X2APIC; } + } else if (function == 6 && reg == R_EAX) { + ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ } else if (function == 0x80000001 && reg == R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: -- 2.1.4 [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v2] i386: Introduce ARAT CPU feature 2015-05-25 14:06 ` [Qemu-devel] [PATCH v2] " Jan Kiszka @ 2015-05-25 14:16 ` Paolo Bonzini 2015-05-25 18:03 ` Eduardo Habkost 0 siblings, 1 reply; 7+ messages in thread From: Paolo Bonzini @ 2015-05-25 14:16 UTC (permalink / raw) To: Jan Kiszka, Eduardo Habkost; +Cc: qemu-devel, kvm On 25/05/2015 16:06, Jan Kiszka wrote: > static void pc_compat_2_3(MachineState *machine) > { > + x86_cpu_compat_set_features("Westmere", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); > + x86_cpu_compat_set_features("SandyBridge", FEAT_6_EAX, 0, > + CPUID_6_EAX_ARAT); > + x86_cpu_compat_set_features("IvyBridge", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); > + x86_cpu_compat_set_features("Haswell-noTSX", FEAT_6_EAX, 0, > + CPUID_6_EAX_ARAT); > + x86_cpu_compat_set_features("Haswell", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); > + x86_cpu_compat_set_features("Broadwell-noTSC", FEAT_6_EAX, 0, > + CPUID_6_EAX_ARAT); noTSX. Also, I think this doesn't cover Q35. Eduardo has patches to clean that up so that (I think) less duplication is required. Paolo > + x86_cpu_compat_set_features("Broadwell", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); > } > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v2] i386: Introduce ARAT CPU feature 2015-05-25 14:16 ` Paolo Bonzini @ 2015-05-25 18:03 ` Eduardo Habkost [not found] ` <5563F821.7080202@web.de> 0 siblings, 1 reply; 7+ messages in thread From: Eduardo Habkost @ 2015-05-25 18:03 UTC (permalink / raw) To: Paolo Bonzini; +Cc: Jan Kiszka, qemu-devel, kvm On Mon, May 25, 2015 at 04:16:14PM +0200, Paolo Bonzini wrote: > On 25/05/2015 16:06, Jan Kiszka wrote: > > static void pc_compat_2_3(MachineState *machine) > > { > > + x86_cpu_compat_set_features("Westmere", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); > > + x86_cpu_compat_set_features("SandyBridge", FEAT_6_EAX, 0, > > + CPUID_6_EAX_ARAT); > > + x86_cpu_compat_set_features("IvyBridge", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); > > + x86_cpu_compat_set_features("Haswell-noTSX", FEAT_6_EAX, 0, > > + CPUID_6_EAX_ARAT); > > + x86_cpu_compat_set_features("Haswell", FEAT_6_EAX, 0, CPUID_6_EAX_ARAT); > > + x86_cpu_compat_set_features("Broadwell-noTSC", FEAT_6_EAX, 0, > > + CPUID_6_EAX_ARAT); > > noTSX. > > Also, I think this doesn't cover Q35. Eduardo has patches to clean that > up so that (I think) less duplication is required. pc_compat_*() removal/deduplication will require a few PC cleanup series to be included first, so it may take a while. But PC_COMPAT_* is not duplicated, and with the feature flag property patch that is now in the x86 tree[1], you can use PC_COMPAT_2_3[2] to do the above, with something like: { .driver = TYPE_X86_CPU, .property = "arat", .value = "off" }, (As no CPU model had ARAT enabled in QEMU 2.3, setting it to off on TYPE_X86_CPU is simpler than enumerating the CPU models above). [1] https://github.com/ehabkost/qemu.git x86 [2] The following series defines PC_COMPAT_2_3: [PATCH v2 00/13] pc, hw, spapr: Cleanup of {HW, PC, SPAPR}_COMPAT_* macros -- Eduardo ^ permalink raw reply [flat|nested] 7+ messages in thread
[parent not found: <5563F821.7080202@web.de>]
* Re: [Qemu-devel] [PATCH v4] i386: Introduce ARAT CPU feature [not found] ` <5563F821.7080202@web.de> @ 2015-05-26 17:18 ` Eduardo Habkost 2015-05-26 17:25 ` Eduardo Habkost 0 siblings, 1 reply; 7+ messages in thread From: Eduardo Habkost @ 2015-05-26 17:18 UTC (permalink / raw) To: Jan Kiszka; +Cc: Paolo Bonzini, qemu-devel, kvm, Michael S. Tsirkin (Fixing subject line) On Tue, May 26, 2015 at 06:35:45AM +0200, Jan Kiszka wrote: > From: Jan Kiszka <jan.kiszka@siemens.com> > > ARAT signals that the APIC timer does not stop in power saving states. > As our APICs are emulated, it's fine to expose this feature to guests, > at least when asking for KVM host features or with CPU types that > include the flag. The exact model number that introduced the feature is > not known, but reports can be found that it's at least available since > Sandy Bridge. > > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > --- > > Changes in v4: > - followed suggestions by Eduardo, now using PC_COMPAT_2_3 define > > hw/i386/pc_piix.c | 4 ++++ > hw/i386/pc_q35.c | 4 ++++ > include/hw/i386/pc.h | 8 ++++++++ > target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- > target-i386/cpu.h | 3 +++ > target-i386/kvm.c | 2 ++ > 6 files changed, 53 insertions(+), 1 deletion(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 212e263..b675d2c 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -543,6 +543,10 @@ static QEMUMachine pc_i440fx_machine_v2_3 = { > PC_I440FX_2_3_MACHINE_OPTIONS, > .name = "pc-i440fx-2.3", > .init = pc_init_pci_2_3, > + .compat_props = (GlobalProperty[]) { > + PC_COMPAT_2_3, > + { /* end of list */ } > + }, > }; > > #define PC_I440FX_2_2_MACHINE_OPTIONS PC_I440FX_2_3_MACHINE_OPTIONS > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index e67f2de..38c3cf2 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -439,6 +439,10 @@ static QEMUMachine pc_q35_machine_v2_3 = { > PC_Q35_2_3_MACHINE_OPTIONS, > .name = "pc-q35-2.3", > .init = pc_q35_init_2_3, > + .compat_props = (GlobalProperty[]) { > + PC_COMPAT_2_3, > + { /* end of list */ } > + }, > }; This breaks pc-*-2.2 and pc-*-2.1, because 2.2 nas no .compat_props set, and 2.1 has .compat_props = HW_COMPAT_2_1. Those issues are fixed by the series: [PATCH v2 00/13] pc, hw, spapr: Cleanup of {HW, PC, SPAPR}_COMPAT_* macros I suggest we base this patch on top of it. -- Eduardo ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v4] i386: Introduce ARAT CPU feature 2015-05-26 17:18 ` [Qemu-devel] [PATCH v4] " Eduardo Habkost @ 2015-05-26 17:25 ` Eduardo Habkost 0 siblings, 0 replies; 7+ messages in thread From: Eduardo Habkost @ 2015-05-26 17:25 UTC (permalink / raw) To: Jan Kiszka; +Cc: Paolo Bonzini, qemu-devel, kvm, Michael S. Tsirkin On Tue, May 26, 2015 at 02:18:32PM -0300, Eduardo Habkost wrote: > (Fixing subject line) > > On Tue, May 26, 2015 at 06:35:45AM +0200, Jan Kiszka wrote: > > From: Jan Kiszka <jan.kiszka@siemens.com> > > > > ARAT signals that the APIC timer does not stop in power saving states. > > As our APICs are emulated, it's fine to expose this feature to guests, > > at least when asking for KVM host features or with CPU types that > > include the flag. The exact model number that introduced the feature is > > not known, but reports can be found that it's at least available since > > Sandy Bridge. > > > > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > > --- > > > > Changes in v4: > > - followed suggestions by Eduardo, now using PC_COMPAT_2_3 define > > > > hw/i386/pc_piix.c | 4 ++++ > > hw/i386/pc_q35.c | 4 ++++ > > include/hw/i386/pc.h | 8 ++++++++ > > target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- > > target-i386/cpu.h | 3 +++ > > target-i386/kvm.c | 2 ++ > > 6 files changed, 53 insertions(+), 1 deletion(-) > > > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > > index 212e263..b675d2c 100644 > > --- a/hw/i386/pc_piix.c > > +++ b/hw/i386/pc_piix.c > > @@ -543,6 +543,10 @@ static QEMUMachine pc_i440fx_machine_v2_3 = { > > PC_I440FX_2_3_MACHINE_OPTIONS, > > .name = "pc-i440fx-2.3", > > .init = pc_init_pci_2_3, > > + .compat_props = (GlobalProperty[]) { > > + PC_COMPAT_2_3, > > + { /* end of list */ } > > + }, > > }; > > > > #define PC_I440FX_2_2_MACHINE_OPTIONS PC_I440FX_2_3_MACHINE_OPTIONS > > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > > index e67f2de..38c3cf2 100644 > > --- a/hw/i386/pc_q35.c > > +++ b/hw/i386/pc_q35.c > > @@ -439,6 +439,10 @@ static QEMUMachine pc_q35_machine_v2_3 = { > > PC_Q35_2_3_MACHINE_OPTIONS, > > .name = "pc-q35-2.3", > > .init = pc_q35_init_2_3, > > + .compat_props = (GlobalProperty[]) { > > + PC_COMPAT_2_3, > > + { /* end of list */ } > > + }, > > }; > > This breaks pc-*-2.2 and pc-*-2.1, because 2.2 nas no .compat_props set, > and 2.1 has .compat_props = HW_COMPAT_2_1. > > Those issues are fixed by the series: > [PATCH v2 00/13] pc, hw, spapr: Cleanup of {HW, PC, SPAPR}_COMPAT_* macros > > I suggest we base this patch on top of it. For reference, the PC compat series I have submitted recently are available on git, at: git://github.com/ehabkost/qemu-hacks.git work/pc-compat-cleanup2 (Subject: pc, hw, spapr: Cleanup of {HW, PC, SPAPR}_COMPAT_* macros) git://github.com/ehabkost/qemu-hacks.git work/pc-compat-macros (Subject: pc: Don't use QEMUMachine, simplify compat+init code) -- Eduardo ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-05-26 17:25 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2015-05-24 15:16 [Qemu-devel] [PATCH] i386: Introduce ARAT CPU feature Jan Kiszka
2015-05-25 13:23 ` Paolo Bonzini
2015-05-25 14:06 ` [Qemu-devel] [PATCH v2] " Jan Kiszka
2015-05-25 14:16 ` Paolo Bonzini
2015-05-25 18:03 ` Eduardo Habkost
[not found] ` <5563F821.7080202@web.de>
2015-05-26 17:18 ` [Qemu-devel] [PATCH v4] " Eduardo Habkost
2015-05-26 17:25 ` Eduardo Habkost
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