From: "Andreas Färber" <afaerber@suse.de>
To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
Paolo Bonzini <pbonzini@redhat.com>,
leon.alrae@imgtec.com, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v5 2/3] softmmu: Add probe_write()
Date: Tue, 26 May 2015 18:58:49 +0200 [thread overview]
Message-ID: <5564A649.6070206@suse.de> (raw)
In-Reply-To: <1432658961-48553-3-git-send-email-yongbok.kim@imgtec.com>
Am 26.05.2015 um 18:49 schrieb Yongbok Kim:
> Add probe_write() forces a tlb_fill if the specified guest virtual
> index isn't in the TCG softmmu TLB.
>
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
> include/exec/exec-all.h | 2 ++
> softmmu_template.h | 20 ++++++++++++++++++++
> 2 files changed, 22 insertions(+), 0 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index b58cd47..af51203 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -109,6 +109,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
> hwaddr paddr, MemTxAttrs attrs,
> int prot, int mmu_idx, target_ulong size);
> void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
> +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
> + uintptr_t retaddr);
> #else
> static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> diff --git a/softmmu_template.h b/softmmu_template.h
> index 9cb1659..1a1de4a 100644
> --- a/softmmu_template.h
> +++ b/softmmu_template.h
> @@ -548,6 +548,26 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
> helper_te_st_name(env, addr, val, oi, GETRA());
> }
>
> +#if DATA_SIZE == 1
> +/*
> + * Force a tlb_fill if the specified guest virtual index isn't in the TCG
> + * softmmu TLB.
> + */
> +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
> + uintptr_t retaddr)
> +{
> + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> +
> + if ((addr & TARGET_PAGE_MASK)
> + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
> + /* TLB entry is for a different page */
> + if (!VICTIM_TLB_HIT(addr_write)) {
> + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
Isn't the use of ENV_GET_CPU() here contradicting Peter C.'s series?
Regards,
Andreas
> + }
> + }
> +}
> +#endif
> #endif /* !defined(SOFTMMU_CODE_ACCESS) */
>
> #undef READ_ACCESS_TYPE
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB
21284 (AG Nürnberg)
next prev parent reply other threads:[~2015-05-26 16:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-26 16:49 [Qemu-devel] [PATCH v5 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
2015-05-26 16:49 ` [Qemu-devel] [PATCH v5 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
2015-05-26 16:49 ` [Qemu-devel] [PATCH v5 2/3] softmmu: Add probe_write() Yongbok Kim
2015-05-26 16:53 ` Peter Maydell
2015-05-26 17:33 ` Richard Henderson
2015-05-27 9:17 ` Yongbok Kim
2015-05-26 16:58 ` Andreas Färber [this message]
2015-05-26 17:16 ` Paolo Bonzini
2015-05-26 17:19 ` Peter Crosthwaite
2015-05-26 16:49 ` [Qemu-devel] [PATCH v5 3/3] target-mips: Misaligned memory accesses for MSA Yongbok Kim
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