From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyJVl-0007rc-Qo for qemu-devel@nongnu.org; Fri, 29 May 2015 08:35:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyJVi-0000d7-9R for qemu-devel@nongnu.org; Fri, 29 May 2015 08:35:41 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:1027) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyJVi-0000cs-4T for qemu-devel@nongnu.org; Fri, 29 May 2015 08:35:38 -0400 Message-ID: <55685C94.6020009@imgtec.com> Date: Fri, 29 May 2015 13:33:24 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1432733342-64176-1-git-send-email-yongbok.kim@imgtec.com> <1432733342-64176-2-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1432733342-64176-2-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v6 1/3] target-mips: Misaligned memory accesses for R6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, afaerber@suse.de, rth@twiddle.net On 27/05/2015 14:29, Yongbok Kim wrote: > @@ -2143,7 +2146,8 @@ static void gen_ld(DisasContext *ctx, uint32_t op= c, > t1 =3D tcg_const_tl(pc_relative_pc(ctx)); > gen_op_addr_add(ctx, t0, t0, t1); > tcg_temp_free(t1); > - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); > + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | > + ctx->default_tcg_memop_mask); > gen_store_gpr(t0, rt); > opn =3D "ldpc"; > break; > @@ -2152,22 +2156,26 @@ static void gen_ld(DisasContext *ctx, uint32_t = opc, > t1 =3D tcg_const_tl(pc_relative_pc(ctx)); > gen_op_addr_add(ctx, t0, t0, t1); > tcg_temp_free(t1); > - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); > + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | > + ctx->default_tcg_memop_mask); > gen_store_gpr(t0, rt); > opn =3D "lwpc"; > break; As I can see in other places you skipped load/store instructions not present in R6 spec (like pre-R6 DSP or microMIPS loads/stores), which probably is fine. However, IIUC these two instructions LWPC and LDPC are from mips16 ASE, so probably you want to skip them as well? (note that for R6 we=92ve got R6_OPC_LWPC and R6_OPC_LDPC and they are naturally aligned). Apart from that, Reviewed-by: Leon Alrae BTW these OPC_LWPC and OPC_LDPC are very confusing... I presume these fake instructions were created in order to reuse gen_ldst() function for mips16 M16_OPC_LWPC and I64_LDPC instructions. It would be nice to clean this up at some point (the same as OPC_JALRC). Leon