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Date: Mon, 01 Jun 2015 10:22:10 +0200
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Subject: Re: [Qemu-devel] [RFC v2 25/34] arm: enable multi-arch
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To: Peter Crosthwaite <crosthwaitepeter@gmail.com>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, rth@twiddle.net, edgar.iglesias@gmail.com, afaerber@suse.de, Peter Crosthwaite <crosthwaite.peter@gmail.com>



On 31/05/2015 08:11, Peter Crosthwaite wrote:
> +#ifndef TARGET_MULTI
> +
>  #define EXCP_UDEF            1   /* undefined instruction */
>  #define EXCP_SWI             2   /* software interrupt */
>  #define EXCP_PREFETCH_ABORT  3
> @@ -57,6 +71,10 @@
>  #define EXCP_VIRQ           14
>  #define EXCP_VFIQ           15
>  
> +#endif /* TARGET_MULTI */

Separate header for stuff private to target-arm?

> +/* These defs are public as needed by ARMv7M NVIC */
> +
>  #define ARMV7M_EXCP_RESET   1
>  #define ARMV7M_EXCP_NMI     2
>  #define ARMV7M_EXCP_HARD    3
> @@ -73,6 +91,8 @@
>  #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
>  #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
>  
> +#ifndef TARGET_MULTI
> +
>  /* The usual mapping for an AArch64 system register to its AArch32
>   * counterpart is for the 32 bit world to have access to the lower
>   * half only (with writes leaving the upper half untouched). It's
> @@ -87,6 +107,8 @@
>  #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
>  #endif
>  
> +#endif /* !TARGET_MULTI */
> +
>  /* Meanings of the ARMCPU object's four inbound GPIO lines */
>  #define ARM_CPU_IRQ 0
>  #define ARM_CPU_FIQ 1
> @@ -95,6 +117,7 @@
>  
>  struct arm_boot_info;
>  
> +#undef NB_MMU_MODES

Perhaps do this for all targets, even if they compile just fine without
it?  You had a similar case in patch 2 ("FIXME: apply target-foo change
pattern to all archs").

Paolo

>  #define NB_MMU_MODES 7