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From: Shannon Zhao <shannon.zhao@linaro.org>
To: Sergey Fedorov <serge.fdrv@gmail.com>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [Qemu-devel] [PATCH] target-arm: fix REVIDR reset value
Date: Tue, 02 Jun 2015 20:51:24 +0800	[thread overview]
Message-ID: <556DA6CC.6040802@linaro.org> (raw)
In-Reply-To: <1433247661-2555-1-git-send-email-serge.fdrv@gmail.com>

Hi,

On 2015/6/2 20:21, Sergey Fedorov wrote:
> According to ARM Cortex-A57 TRM, REVIDR reset value should be zero. So
> let REVIDR reset value be specified by CPU model and fix it for
> Cortex-A57.
> 

Also need to fix it for Cortex-A53?

> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
>  target-arm/cpu-qom.h | 1 +
>  target-arm/cpu64.c   | 1 +
>  target-arm/helper.c  | 2 +-
>  3 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> index ed5a644..c80381d 100644
> --- a/target-arm/cpu-qom.h
> +++ b/target-arm/cpu-qom.h
> @@ -127,6 +127,7 @@ typedef struct ARMCPU {
>       * prefix means a constant register.
>       */
>      uint32_t midr;
> +    uint32_t revidr;
>      uint32_t reset_fpsid;
>      uint32_t mvfr0;
>      uint32_t mvfr1;
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index bf7dd68..e330160 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -110,6 +110,7 @@ static void aarch64_a57_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_CRC);
>      cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
>      cpu->midr = 0x411fd070;
> +    cpu->revidr = 0x00000000;
>      cpu->reset_fpsid = 0x41034070;
>      cpu->mvfr0 = 0x10110222;
>      cpu->mvfr1 = 0x12111111;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b2b377a..89940d6 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3363,7 +3363,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>                .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
>              { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
>                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
> -              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
> +              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
>              REGINFO_SENTINEL
>          };
>          ARMCPRegInfo id_cp_reginfo[] = {
> 

-- 
Shannon

  reply	other threads:[~2015-06-02 12:51 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-02 12:21 [Qemu-devel] [PATCH] target-arm: fix REVIDR reset value Sergey Fedorov
2015-06-02 12:51 ` Shannon Zhao [this message]
2015-06-02 13:18   ` Peter Maydell
2015-06-02 13:28     ` Peter Maydell
2015-06-03  7:40       ` Sergey Fedorov
2015-06-02 13:54 ` Peter Maydell
2015-06-03  7:42   ` Sergey Fedorov

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