From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzlfP-0001z8-NX for qemu-devel@nongnu.org; Tue, 02 Jun 2015 08:51:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzlfK-0006MR-BV for qemu-devel@nongnu.org; Tue, 02 Jun 2015 08:51:39 -0400 Received: from mail-ob0-f179.google.com ([209.85.214.179]:36708) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzlfK-0006LG-3P for qemu-devel@nongnu.org; Tue, 02 Jun 2015 08:51:34 -0400 Received: by obbea2 with SMTP id ea2so126675227obb.3 for ; Tue, 02 Jun 2015 05:51:33 -0700 (PDT) Message-ID: <556DA6CC.6040802@linaro.org> Date: Tue, 02 Jun 2015 20:51:24 +0800 From: Shannon Zhao MIME-Version: 1.0 References: <1433247661-2555-1-git-send-email-serge.fdrv@gmail.com> In-Reply-To: <1433247661-2555-1-git-send-email-serge.fdrv@gmail.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-arm: fix REVIDR reset value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov , qemu-devel@nongnu.org Cc: Peter Maydell Hi, On 2015/6/2 20:21, Sergey Fedorov wrote: > According to ARM Cortex-A57 TRM, REVIDR reset value should be zero. So > let REVIDR reset value be specified by CPU model and fix it for > Cortex-A57. > Also need to fix it for Cortex-A53? > Signed-off-by: Sergey Fedorov > --- > target-arm/cpu-qom.h | 1 + > target-arm/cpu64.c | 1 + > target-arm/helper.c | 2 +- > 3 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h > index ed5a644..c80381d 100644 > --- a/target-arm/cpu-qom.h > +++ b/target-arm/cpu-qom.h > @@ -127,6 +127,7 @@ typedef struct ARMCPU { > * prefix means a constant register. > */ > uint32_t midr; > + uint32_t revidr; > uint32_t reset_fpsid; > uint32_t mvfr0; > uint32_t mvfr1; > diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c > index bf7dd68..e330160 100644 > --- a/target-arm/cpu64.c > +++ b/target-arm/cpu64.c > @@ -110,6 +110,7 @@ static void aarch64_a57_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_CRC); > cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; > cpu->midr = 0x411fd070; > + cpu->revidr = 0x00000000; > cpu->reset_fpsid = 0x41034070; > cpu->mvfr0 = 0x10110222; > cpu->mvfr1 = 0x12111111; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index b2b377a..89940d6 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3363,7 +3363,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, > { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, > - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, > + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, > REGINFO_SENTINEL > }; > ARMCPRegInfo id_cp_reginfo[] = { > -- Shannon