From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzp72-0007l5-EW for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:32:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yzp6x-00006g-AT for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:32:24 -0400 Received: from mail-qc0-x22b.google.com ([2607:f8b0:400d:c01::22b]:35323) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzp6x-00006c-72 for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:32:19 -0400 Received: by qczw4 with SMTP id w4so37399375qcz.2 for ; Tue, 02 Jun 2015 09:32:18 -0700 (PDT) Sender: Richard Henderson Message-ID: <556DDA8D.8040508@twiddle.net> Date: Tue, 02 Jun 2015 09:32:13 -0700 From: Richard Henderson MIME-Version: 1.0 References: <556CA71D.4090208@twiddle.net> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 09/10 v11] target-tilegx: Generate tcg instructions to finish "Hello world" List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Chen Gang , Peter Maydell , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , Chris Metcalf Cc: "walt@tilera.com" , Riku Voipio , qemu-devel On 06/01/2015 01:54 PM, Chen Gang wrote: >> Further, the < TILEGX_R_COUNT restriction is also incorrect. True, you don't >> actually implement the top 7 special registers, but that doesn't matter, you >> should still be incrementing them. >> > > We did not implement them, so can not increment them, either. > > They are hidden to outside, or we have to define and implement them. > > So for me, the current code is correct. It isn't correct, it's simply functional. These registers may eventually be implemented, and at that point this code will fail. You'll note that your store_add functions don't have the same problem, because they don't have this R_COUNT check. It would be better to increase the number of buffer slots and do the right thing here in load_add. My suggestion is to expand tmp_regs to 4, drop tmp_regcur, and have dest_gr manage all of the indexing. I.e. static TCGv dest_gr(DisasContext *dc, uint8_t rdst) { int n = dc->n_tmp_regs++; assert(n < ARRAY_SIZE(dc->tmp_regs)); dc->tmp_regs[n].idx = rdst; return dc->tmp_regs[n].val = tcg_temp_new_i64(); } In this way you can in fact call dest_gr twice within load_add and everything will Just Work. r~