From: Christopher Covington <cov@codeaurora.org>
To: Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PULL 1/8] target-sh4: use bit number for SR constants
Date: Tue, 02 Jun 2015 19:01:31 -0400 [thread overview]
Message-ID: <556E35CB.3070703@codeaurora.org> (raw)
In-Reply-To: <1433194188-24514-2-git-send-email-aurelien@aurel32.net>
Hi Aurelien,
On 06/01/2015 05:29 PM, Aurelien Jarno wrote:
> Use the bit number for SR constants instead of using a bit mask. This
> make possible to also use the constants for shifts.
>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
> target-sh4/cpu.c | 3 +-
> target-sh4/cpu.h | 30 ++++++++++----------
> target-sh4/gdbstub.c | 4 +--
> target-sh4/helper.c | 27 +++++++++---------
> target-sh4/op_helper.c | 26 ++++++++---------
> target-sh4/translate.c | 75 ++++++++++++++++++++++++++------------------------
> 6 files changed, 85 insertions(+), 80 deletions(-)
>
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index d187a2b..cccb14f 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -61,7 +61,8 @@ static void superh_cpu_reset(CPUState *s)
> env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
> set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
> #else
> - env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
> + env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
> + (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
I like using the BIT() macro for this kind of thing.
Chris
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-06-02 23:01 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-01 21:29 [Qemu-devel] [PULL 0/8] SH4 patches for upstream Aurelien Jarno
2015-06-01 21:29 ` [Qemu-devel] [PULL 1/8] target-sh4: use bit number for SR constants Aurelien Jarno
2015-06-02 23:01 ` Christopher Covington [this message]
2015-06-03 7:09 ` Aurelien Jarno
2015-06-03 14:34 ` Aurelien Jarno
2015-06-03 14:46 ` Peter Maydell
2015-06-01 21:29 ` [Qemu-devel] [PULL 2/8] target-sh4: Split out T from SR Aurelien Jarno
2015-06-01 21:29 ` [Qemu-devel] [PULL 3/8] target-sh4: optimize addc using add2 Aurelien Jarno
2015-06-01 21:29 ` [Qemu-devel] [PULL 4/8] target-sh4: optimize subc using sub2 Aurelien Jarno
2015-06-01 21:29 ` [Qemu-devel] [PULL 5/8] target-sh4: optimize negc using add2 and sub2 Aurelien Jarno
2015-06-01 21:29 ` [Qemu-devel] [PULL 6/8] target-sh4: split out Q and M from of SR and optimize div1 Aurelien Jarno
2015-06-01 21:29 ` [Qemu-devel] [PULL 7/8] target-sh4: factorize fmov implementation Aurelien Jarno
2015-06-01 21:29 ` [Qemu-devel] [PULL 8/8] target-sh4: remove dead code Aurelien Jarno
2015-06-02 17:23 ` [Qemu-devel] [PULL 0/8] SH4 patches for upstream Peter Maydell
2015-06-02 18:55 ` Aurelien Jarno
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