From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z03Zf-0008Ts-II for qemu-devel@nongnu.org; Wed, 03 Jun 2015 03:58:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z03Zc-0005Yw-C0 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 03:58:55 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55754) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z03Zc-0005Yc-60 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 03:58:52 -0400 Message-ID: <556EB3B8.2020402@redhat.com> Date: Wed, 03 Jun 2015 09:58:48 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <556EA649.3010805@redhat.com> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] On x86 MMU modes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sandhya Kumar Cc: qemu-devel@nongnu.org On 03/06/2015 09:41, Sandhya Kumar wrote: > Thanks for your mail. Are these TLB modes logic specific to QEMU > implementation for x86? Yes, they are specific to QEMU. > Asking this as I am not able to get any information about seperate TLBs > from Intel developer manuals Real hardware TLBs probably work in a completely different (and undocumented) way. Paolo