From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56037) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0NJe-000338-D3 for qemu-devel@nongnu.org; Thu, 04 Jun 2015 01:03:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0NJb-000723-7Z for qemu-devel@nongnu.org; Thu, 04 Jun 2015 01:03:42 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:34408) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0NJa-00071l-Ve for qemu-devel@nongnu.org; Thu, 04 Jun 2015 01:03:39 -0400 Received: by payr10 with SMTP id r10so21708528pay.1 for ; Wed, 03 Jun 2015 22:03:38 -0700 (PDT) Sender: Richard Henderson Message-ID: <556FDC26.9090302@twiddle.net> Date: Wed, 03 Jun 2015 22:03:34 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1432510638-21021-1-git-send-email-aurelien@aurel32.net> <1432510638-21021-4-git-send-email-aurelien@aurel32.net> In-Reply-To: <1432510638-21021-4-git-send-email-aurelien@aurel32.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 3/8] target-sh4: optimize addc using add2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , qemu-devel@nongnu.org On 05/24/2015 04:37 PM, Aurelien Jarno wrote: > - TCGv t0, t1; > - t0 = tcg_temp_new(); > + TCGv t0, t1, t2; > + t0 = tcg_const_tl(0); > t1 = tcg_temp_new(); > - tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8)); > - tcg_gen_add_i32(t1, cpu_sr_t, t0); > - tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), t0); > - tcg_gen_setcond_i32(TCG_COND_GTU, t0, t0, t1); > - tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0); > + t2 = tcg_temp_new(); > + tcg_gen_add2_i32(t1, t2, REG(B11_8), t0, REG(B7_4), t0); > + tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, t1, t2, cpu_sr_t, t0); Swap these two adds and you don't need t2. You can consume sr_t immediately and start producing it in the same go. r~