From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:56348)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1Z0NLG-00044L-HJ
	for qemu-devel@nongnu.org; Thu, 04 Jun 2015 01:05:23 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1Z0NLC-0007p1-L4
	for qemu-devel@nongnu.org; Thu, 04 Jun 2015 01:05:22 -0400
Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:34952)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1Z0NLC-0007on-Ex
	for qemu-devel@nongnu.org; Thu, 04 Jun 2015 01:05:18 -0400
Received: by padjw17 with SMTP id jw17so21653598pad.2
	for <qemu-devel@nongnu.org>; Wed, 03 Jun 2015 22:05:17 -0700 (PDT)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <556FDC8A.30206@twiddle.net>
Date: Wed, 03 Jun 2015 22:05:14 -0700
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1432510638-21021-1-git-send-email-aurelien@aurel32.net>
	<1432510638-21021-5-git-send-email-aurelien@aurel32.net>
In-Reply-To: <1432510638-21021-5-git-send-email-aurelien@aurel32.net>
Content-Type: text/plain; charset=windows-1252; format=flowed
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH v3 4/8] target-sh4: optimize subc using sub2
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org

On 05/24/2015 04:37 PM, Aurelien Jarno wrote:
> +            tcg_gen_sub2_i32(t1, t2, REG(B11_8), t0, REG(B7_4), t0);
> +            tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, t1, t2, cpu_sr_t, t0);

Similarly.


r~