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From: Laszlo Ersek <lersek@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
	Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Gerd Hoffmann <kraxel@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v2 13/23] target-i386: create a separate AddressSpace for each CPU
Date: Thu, 04 Jun 2015 14:48:10 +0200	[thread overview]
Message-ID: <5570490A.8050203@redhat.com> (raw)
In-Reply-To: <5570060E.5070101@redhat.com>

On 06/04/15 10:02, Paolo Bonzini wrote:
> 
> 
> On 03/06/2015 19:58, Peter Crosthwaite wrote:
>> On Wed, Jun 3, 2015 at 10:08 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>>> Different CPUs can be in SMM or not at the same time, thus they
>>> will see different things where the chipset places SMRAM.
>>>
>>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>>> ---
>>>  target-i386/cpu-qom.h |  1 +
>>>  target-i386/cpu.c     | 14 ++++++++++++++
>>>  2 files changed, 15 insertions(+)
>>>
>>> diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
>>> index 31a0c1e..39cd878 100644
>>> --- a/target-i386/cpu-qom.h
>>> +++ b/target-i386/cpu-qom.h
>>> @@ -111,6 +111,7 @@ typedef struct X86CPU {
>>>      /* in order to simplify APIC support, we leave this pointer to the
>>>         user */
>>>      struct DeviceState *apic_state;
>>> +    struct MemoryRegion *cpu_as_root;
>>>  } X86CPU;
>>>
>>>  static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
>>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
>>> index 523d0cd..23b57a9 100644
>>> --- a/target-i386/cpu.c
>>> +++ b/target-i386/cpu.c
>>> @@ -44,6 +44,7 @@
>>>  #include "hw/qdev-properties.h"
>>>  #include "hw/cpu/icc_bus.h"
>>>  #ifndef CONFIG_USER_ONLY
>>> +#include "exec/address-spaces.h"
>>>  #include "hw/xen/xen.h"
>>>  #include "hw/i386/apic_internal.h"
>>>  #endif
>>> @@ -2811,6 +2812,18 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
>>>  #endif
>>>
>>>      mce_init(cpu);
>>> +
>>> +#ifndef CONFIG_USER_ONLY
>>> +    if (tcg_enabled()) {
>>> +        cpu->cpu_as_root = g_new(MemoryRegion, 1);
>>> +        cs->as = g_new(AddressSpace, 1);
>>> +        memory_region_init_alias(cpu->cpu_as_root, OBJECT(cpu), "memory",
>>> +                                 get_system_memory(), 0, ~0ull);
>>> +        memory_region_set_enabled(cpu->cpu_as_root, true);
>>> +        address_space_init(cs->as, cpu->cpu_as_root, "CPU");
>>> +    }
>>> +#endif
>>> +
>>>      qemu_init_vcpu(cs);
>>>
>>>      /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
>>> @@ -2834,6 +2847,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
>>>      cpu_reset(cs);
>>>
>>>      xcc->parent_realize(dev, &local_err);
>>> +
>>
>> This intentional?
> 
> It's a remnant from a previous version, but I do prefer having a blank
> line before the error recovery part of a function.

(+1. In fact if it's a cascade of several labels, I might insert a blank
line before each label.)

Laszlo

> 
> Paolo
> 
>> Regards,
>> Peter
>>
>>>  out:
>>>      if (local_err != NULL) {
>>>          error_propagate(errp, local_err);
>>> --
>>> 2.4.1
>>>
>>>
>>>

  reply	other threads:[~2015-06-04 12:48 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-03 17:08 [Qemu-devel] [PATCH v2 00/23] SMM improvements (chipset and TCG parts) Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 01/23] target-i386: introduce cpu_get_mem_attrs Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 02/23] target-i386: Use correct memory attributes for memory accesses Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 03/23] target-i386: Use correct memory attributes for ioport accesses Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 04/23] target-i386: mask NMIs on entry to SMM Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 05/23] target-i386: set G=1 in SMM big real mode selectors Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 06/23] target-i386: wake up processors that receive an SMI Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 07/23] pflash_cfi01: change big-endian property to BIT type Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 08/23] pflash_cfi01: change to new-style MMIO accessors Paolo Bonzini
2015-06-04  6:19   ` Peter Crosthwaite
2015-06-04  8:02     ` Paolo Bonzini
2015-06-04 12:51       ` Laszlo Ersek
2015-06-09 18:08       ` Richard Henderson
2015-06-09 18:47         ` Michael S. Tsirkin
2015-06-17  7:56         ` Paolo Bonzini
2015-06-17  8:22           ` Markus Armbruster
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 09/23] pflash_cfi01: add secure property Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 10/23] vl: allow full-blown QemuOpts syntax for -global Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 11/23] qom: add object_property_add_const_link Paolo Bonzini
2015-06-04  6:33   ` Peter Crosthwaite
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 12/23] vl: run "late" notifiers immediately Paolo Bonzini
2015-06-04  6:39   ` Peter Crosthwaite
2015-06-04  8:03     ` Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 13/23] target-i386: create a separate AddressSpace for each CPU Paolo Bonzini
2015-06-03 17:58   ` Peter Crosthwaite
2015-06-04  8:02     ` Paolo Bonzini
2015-06-04 12:48       ` Laszlo Ersek [this message]
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 14/23] hw/i386: add a separate region that tracks the SMRAME bit Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 15/23] target-i386: use memory API to implement SMRAM Paolo Bonzini
2015-06-04  7:19   ` Peter Crosthwaite
2015-06-04  8:05     ` Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 16/23] hw/i386: remove smram_update Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 17/23] q35: implement high SMRAM Paolo Bonzini
2015-06-04 12:50   ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 18/23] q35: fix ESMRAMC default Paolo Bonzini
2015-06-04 12:51   ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 19/23] q35: add config space wmask for SMRAM and ESMRAMC Paolo Bonzini
2015-06-04 12:51   ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 20/23] q35: implement SMRAM.D_LCK Paolo Bonzini
2015-06-04 12:51   ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 21/23] q35: add test for SMRAM.D_LCK Paolo Bonzini
2015-06-04 12:52   ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 22/23] q35: implement TSEG Paolo Bonzini
2015-06-04 12:53   ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 23/23] ich9: implement SMI_LOCK Paolo Bonzini
2015-06-04 12:53   ` Michael S. Tsirkin
2015-06-03 17:41 ` [Qemu-devel] [PATCH v2 00/23] SMM improvements (chipset and TCG parts) Laszlo Ersek
2015-06-03 17:44   ` Paolo Bonzini
2015-06-04 12:54 ` Michael S. Tsirkin

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