From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0xbp-0008Hf-Be for qemu-devel@nongnu.org; Fri, 05 Jun 2015 15:48:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0xbk-0003jn-Ct for qemu-devel@nongnu.org; Fri, 05 Jun 2015 15:48:53 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:20094) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0xbk-0003ir-6s for qemu-devel@nongnu.org; Fri, 05 Jun 2015 15:48:48 -0400 Message-ID: <5571FD16.9000905@imgtec.com> Date: Fri, 5 Jun 2015 20:48:38 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1433323956-7867-1-git-send-email-leon.alrae@imgtec.com> <1433323956-7867-2-git-send-email-leon.alrae@imgtec.com> <20150604221406.GB6313@aurel32.net> In-Reply-To: <20150604221406.GB6313@aurel32.net> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 1/7] target-mips: extend selected CP0 registers to 64-bits in MIPS32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: james.hogan@imgtec.com, qemu-devel@nongnu.org On 04/06/15 23:14, Aurelien Jarno wrote: > If you change the size of these registers, you have to adjust the > corresponding MFC0 function for MIPS32, as the tcg_gen_ld_tl() function > will point to the wrong side of the field on big endian hosts. I'll fix it, thanks for pointing this out. Leon