From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com
Subject: Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b
Date: Fri, 2 Aug 2024 16:45:00 +1000 [thread overview]
Message-ID: <5580439d-08ed-483c-aecf-e31536f36f79@linaro.org> (raw)
In-Reply-To: <b65aa4d1-c206-4ebb-af8c-75b034c6b875@linux.alibaba.com>
On 8/2/24 16:21, LIU Zhiwei wrote:
> By the way, the MXL is const now in recently updated RISC-V specification.
Oh yes? Then perhaps we should rename misa_mxl_max to misa_mxl.
r~
next prev parent reply other threads:[~2024-08-02 6:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-02 3:16 [PATCH v2 0/3] target/riscv: Remove redundant insn length check for zama16b LIU Zhiwei
2024-08-02 3:16 ` [PATCH v2 1/3] " LIU Zhiwei
2024-08-02 5:38 ` Richard Henderson
2024-08-02 6:31 ` LIU Zhiwei
2024-08-02 3:16 ` [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b LIU Zhiwei
2024-08-02 5:47 ` Richard Henderson
2024-08-02 6:21 ` LIU Zhiwei
2024-08-02 6:45 ` Richard Henderson [this message]
2024-08-02 6:53 ` LIU Zhiwei
2024-08-02 6:42 ` LIU Zhiwei
2024-08-02 6:46 ` Richard Henderson
2024-08-02 3:16 ` [PATCH v2 3/3] target/riscv: Relax fld alignment requirement LIU Zhiwei
2024-08-02 5:52 ` Richard Henderson
2024-08-02 6:27 ` LIU Zhiwei
2024-08-02 6:49 ` Richard Henderson
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