From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5pOy-00049r-3F for qemu-devel@nongnu.org; Fri, 19 Jun 2015 02:03:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5pOu-0004cV-Ub for qemu-devel@nongnu.org; Fri, 19 Jun 2015 02:03:44 -0400 Received: from icp-osb-irony-out8.external.iinet.net.au ([203.59.1.225]:42519) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5pOu-0004bI-HR for qemu-devel@nongnu.org; Fri, 19 Jun 2015 02:03:40 -0400 Message-ID: <5583B0F4.80906@uclinux.org> Date: Fri, 19 Jun 2015 16:04:36 +1000 From: Greg Ungerer MIME-Version: 1.0 References: <1408426627-12071-1-git-send-email-gerg@uclinux.org> <1408426627-12071-2-git-send-email-gerg@uclinux.org> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/3] m68k: implmenent more ColdFire 5208 interrupt controller functionality List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: "qemu-devel@nongnu.org Developers" Hi Peter, On 19/06/15 15:24, Peter Crosthwaite wrote: > On Mon, Aug 18, 2014 at 10:37 PM, wrote: >> From: Greg Ungerer >> >> Implement the SIMR and CIMR registers of the 5208 interrupt controller. >> These are used by modern versions of Linux running on ColdFire (not sure >> of the exact version they were introduced, but they have been in for quite >> a while now). >> >> Without this change when attempting to run a linux-3.5 kernel you will >> see: >> >> qemu: hardware error: mcf_intc_write: Bad write offset 28 >> >> and execution will stop and dump out. >> >> Signed-off-by: Greg Ungerer >> --- >> hw/m68k/mcf_intc.c | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c >> index 621423c..37a9de0 100644 >> --- a/hw/m68k/mcf_intc.c >> +++ b/hw/m68k/mcf_intc.c >> @@ -102,6 +102,20 @@ static void mcf_intc_write(void *opaque, hwaddr addr, >> case 0x0c: >> s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; >> break; >> + case 0x1c: >> + if (val & 0x40) { >> + s->imr = 0xffffffffffffffffull; > > ~0ull. > > Otherwise, > > Reviewed-by: Peter Crosthwaite Thanks, I'll change that and add the reviewed-by. > This introduces magic numbers which is generally discouraged, by this > device has no macrofication at all so I guess it should be cleaned up > at some stage. Agreed. I stuck to the existing style in this case. Regards Greg >> + } else { >> + s->imr |= (0x1ull << (val & 0x3f)); >> + } >> + break; >> + case 0x1d: >> + if (val & 0x40) { >> + s->imr = 0ull; >> + } else { >> + s->imr &= ~(0x1ull << (val & 0x3f)); >> + } >> + break; >> default: >> hw_error("mcf_intc_write: Bad write offset %d\n", offset); >> break; >> -- >> 1.9.1 >> >> >