Re: [Qemu-devel] [PATCH v2 13/15] target-mips: microMIPS32 R6 Major instructions

[Yongbok Kim <yongbok.kim@imgtec.com>]

On 22/06/2015 13:19, Leon Alrae wrote:
> On 19/06/2015 17:25, Yongbok Kim wrote:
>> @@ -14958,8 +14966,28 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
>>      do_cop1:
>>          gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
>>          break;
>> -    case ADDIUPC:
>> -        {
>> +    case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
>> +        if (ctx->insn_flags & ISA_MIPS32R6) {
>> +            /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
>> +            switch ((ctx->opcode >> 16) & 0x1f) {
>> +            case ADDIUPC_00 ... ADDIUPC_07:
>> +                gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt);
>> +                break;
>> +            case AUIPC:
>> +                gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt);
> 
> According to the manual you should pass "ctx->pc & ~0x3" here. Otherwise the
> patch looks good to me.
> 
> Leon
> 

That's weird to see that in the doc. I've checked the instruction and it
has been confirmed that the instruction is *not* clearing the bottom 2 bits
of the PC. This issue will be corrected in the next doc release.

Regards,
Yongbok