Re: [Qemu-devel] [PATCH v3 06/15] target-mips: raise RI exceptions when FIR.PS = 0

[Yongbok Kim <yongbok.kim@imgtec.com>]

On 24/06/2015 13:28, Aurelien Jarno wrote:
> On 2015-06-23 16:38, Yongbok Kim wrote:
>> 64-bit paired-single (PS) floating point data type is optional in the
>> pre-Release 6.
>> It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
>> (The PS data type is removed in the Release 6.)
>>
>> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
>> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
>> ---

> 
> This change means that the PS instructions are now enabled only when
> FCR0_PS is set, instead of being enabled when the FPU in 64-bit mode.
> Have you checked if we need to update a few CPU definitions for it to
> work? I am thinking for example about all the CPU with FCR0_F64, but
> without FCR0_PS.
> 
> Otherwise the patch looks fine to me.
> 

I just checked all the core definitions. All other cores are OK and even
the patch brought some corrections of behaviour like 24Kf shouldn't support
PS data type but it was wrongly enabled.
However Loongson-2E and Loongson-2F might be broken because of the patch.
The question is that how to allow ps data type for these Loongson cores as
in the MIPS III architecture all the those FCR0 field is reserved apart
from implementation and revision numbers.
(1) I could add few more line in check_ps() to allow Loongson according to
the Implementation and Revision numbers. (2) Otherwise updating the
reserved fields against later architectures - F64/PS/D/S. Perhaps that
would cause another problem if an application is expecting all zeroes on
the field.
What do you think?

Regards,
Yongbok