From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z8W4l-0007dc-T1 for qemu-devel@nongnu.org; Fri, 26 Jun 2015 12:02:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z8W4j-0002b4-8c for qemu-devel@nongnu.org; Fri, 26 Jun 2015 12:01:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57823) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z8W4j-0002at-3a for qemu-devel@nongnu.org; Fri, 26 Jun 2015 12:01:57 -0400 References: <1435330053-18733-1-git-send-email-fred.konrad@greensocs.com> <1435330053-18733-16-git-send-email-fred.konrad@greensocs.com> <558D6C7E.6020905@redhat.com> <558D75D0.6060906@greensocs.com> From: Paolo Bonzini Message-ID: <558D776E.20705@redhat.com> Date: Fri, 26 Jun 2015 18:01:50 +0200 MIME-Version: 1.0 In-Reply-To: <558D75D0.6060906@greensocs.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH V6 15/18] cpu: introduce tlb_flush*_all. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Frederic Konrad , qemu-devel@nongnu.org, mttcg@greensocs.com Cc: peter.maydell@linaro.org, a.spyridakis@virtualopensystems.com, mark.burton@greensocs.com, agraf@suse.de, alistair.francis@xilinx.com, guillaume.delbergue@greensocs.com, alex.bennee@linaro.org On 26/06/2015 17:54, Frederic Konrad wrote: >> > I think it doesn't requires to be synchronous as each VCPUs only clear > it's own > tlb here: > > void tlb_flush(CPUState *cpu, int flush_global) > { > CPUArchState *env = cpu->env_ptr; > > #if defined(DEBUG_TLB) > printf("tlb_flush:\n"); > #endif > /* must reset current TB so that interrupts cannot modify the > links while we are modifying them */ > cpu->current_tb = NULL; > > memset(env->tlb_table, -1, sizeof(env->tlb_table)); > memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); > memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); > > env->vtlb_index = 0; > env->tlb_flush_addr = -1; > env->tlb_flush_mask = 0; > tlb_flush_count++; > } > > So what happen is: > An arm instruction want to clear tlb of all VCPUs eg: IS version of > TLBIALL. > The VCPU which execute the TLBIALL_IS can't flush tlb of other VCPU. > It will just ask all VCPU thread to exit and to do tlb_flush hence the > async_work. > > Maybe the big issue might be memory barrier instruction here which I didn't > checked. Yeah, ISTR that in some cases you have to wait for other CPUs to invalidate the TLB before proceeding. Maybe it's only when you have a dmb instruction, but it's probably simpler for QEMU to always do it synchronously. Paolo