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From: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>
To: "Andreas Färber" <afaerber@suse.de>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	qemu-devel@nongnu.org
Cc: chen.fan.fnst@cn.fujitsu.com, imammedo@redhat.com,
	ehabkost@redhat.com, izumi.taku@jp.fujitsu.com
Subject: Re: [Qemu-devel] [RESEND PATCH v8 2/4] hw: add a wrapper for registering reset handler
Date: Tue, 30 Jun 2015 14:31:50 +0800	[thread overview]
Message-ID: <559237D6.8000602@cn.fujitsu.com> (raw)
In-Reply-To: <558C3A53.3000901@suse.de>


On 06/26/2015 01:28 AM, Andreas Färber wrote:
> Am 25.06.2015 um 19:00 schrieb Paolo Bonzini:
>> On 25/06/2015 04:17, Zhu Guihua wrote:
>>> Add a wrapper to specify reset order when registering reset handler,
>>> instead of non-obvious initiazation code ordering.
>>>
>>> Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>
>> I'm sorry, this is not really acceptable.  The initialization code
>> ordering is good because it should be okay to run reset handlers in the
>> same order as code is run.  If there are dependencies between reset
>> handlers, a random integer is not a maintainable way to maintain them.
>>
>> Instead, you should have a single reset handler that calls the reset
>> handlers in the right order; for example a qdev bus such as icc_bus
>> always resets children before parents.
>>
>> Are you sure that you want to remove the icc_bus?... What are you
>> gaining exactly by doing so?
> >From my view we would be gaining by making the APIC an integral part
> (child<>) of the CPU in a follow-up step (there's a TODO to make things
> link<>s).
>
> But either way the CPU's existing reset handler should be able to handle
> CPU/APIC interdependencies just fine, somehow. Which is what Eduardo
> said on v6 and v7. (Another alternative he raised was a machine init
> notifier, but I see no code for that after its mention on v7?)

According to Eduardo's suggestions on v7, the simpler way is to add a 
ordering parameter
to qemu_register_reset(), so that we can ensure the order of apic reset 
handler(apic reset
must be after the other devices' reset on x86).

This way will  not influence the initialization code ordering expect 
apic reset.
Can we take this way? or someone have a better one?

Thanks,
Zhu

>
> Cheers,
> Andreas
>

  parent reply	other threads:[~2015-06-30  6:32 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-25  2:17 [Qemu-devel] [RESEND PATCH v8 0/4] remove icc bus/bridge Zhu Guihua
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 1/4] apic: map APIC's MMIO region at each CPU's address space Zhu Guihua
2015-06-25 16:00   ` Andreas Färber
2015-06-25 16:02     ` Paolo Bonzini
2015-06-25 16:10       ` Andreas Färber
2015-06-25 17:02         ` Paolo Bonzini
2015-06-25 17:08           ` Andreas Färber
2015-06-25 17:27             ` Paolo Bonzini
2015-06-25 17:32               ` Peter Maydell
2015-06-25 17:39                 ` Paolo Bonzini
2015-06-26  9:01               ` Igor Mammedov
2015-06-26  9:05                 ` Paolo Bonzini
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 2/4] hw: add a wrapper for registering reset handler Zhu Guihua
2015-06-25 16:57   ` Andreas Färber
2015-06-25 17:00   ` Paolo Bonzini
2015-06-25 17:28     ` Andreas Färber
2015-06-26  9:19       ` Igor Mammedov
2015-06-26 10:05         ` Paolo Bonzini
2015-06-30  6:31       ` Zhu Guihua [this message]
2015-06-30  9:21         ` Igor Mammedov
2015-06-30 10:50           ` Zhu Guihua
2015-06-30 10:55             ` Peter Maydell
2015-06-30 18:38               ` Eduardo Habkost
2015-06-30 10:24         ` Andreas Färber
2015-06-30 18:30           ` Eduardo Habkost
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 3/4] cpu/apic: drop icc bus/bridge Zhu Guihua
2015-06-25 16:44   ` Andreas Färber
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 4/4] icc_bus: drop the unused files Zhu Guihua

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