From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZBuoO-00060Y-Dr for qemu-devel@nongnu.org; Sun, 05 Jul 2015 21:03:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZBuoK-0003gv-CO for qemu-devel@nongnu.org; Sun, 05 Jul 2015 21:03:08 -0400 Received: from mail-la0-x232.google.com ([2a00:1450:4010:c03::232]:34304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZBuoK-0003gr-4E for qemu-devel@nongnu.org; Sun, 05 Jul 2015 21:03:04 -0400 Received: by lagx9 with SMTP id x9so136215234lag.1 for ; Sun, 05 Jul 2015 18:03:03 -0700 (PDT) Message-ID: <5599D3C0.8040807@gmail.com> Date: Mon, 06 Jul 2015 04:02:56 +0300 From: Dmitry Osipenko MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 2/2] arm_mptimer: Respect IT bit state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite , Peter Maydell Cc: Paolo Bonzini , QEMU Developers > v2: Added missed IRQ status update on control register write as per > Peter Crosthwaite comment. Oh, no! Turned out, that is wrong. I wasn't testing that case properly on HW, V1 is correct. Quote from ARM doc "If the timer interrupt is enabled, Interrupt ID 29 is set as Pending in the Interrupt Distributor after the event flag is set." -- Dmitry