[Qemu-devel] [PATCH rebased for-2.4] target-i386: add ABM to Haswell* and Broadwell* CPU models

[Qemu-devel] [PATCH rebased for-2.4] target-i386: add ABM to Haswell* and Broadwell* CPU models

[Paolo Bonzini]

ABM is only implemented as a single instruction set by AMD; all AMD
processors support both instructions or neither. Intel considers POPCNT
as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
ABM flag to indicate support for both POPCNT and LZCNT.  It has to be
added to Haswell and Broadwell because Haswell, by adding LZCNT, has
completed the ABM.

Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
machine types) on an Haswell-EP machine.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 hw/i386/pc_piix.c | 4 ++++
 hw/i386/pc_q35.c  | 4 ++++
 target-i386/cpu.c | 8 ++++----
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 56cdcb9..d9e9987 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -312,6 +312,10 @@ static void pc_compat_2_3(MachineState *machine)
     if (kvm_enabled()) {
         pcms->smm = ON_OFF_AUTO_OFF;
     }
+    x86_cpu_compat_set_features("Haswell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
+    x86_cpu_compat_set_features("Haswell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
+    x86_cpu_compat_set_features("Broadwell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
+    x86_cpu_compat_set_features("Broadwell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
 }
 
 static void pc_compat_2_2(MachineState *machine)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 8aa3a67..a15a1b1 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -295,6 +295,10 @@ static void pc_compat_2_3(MachineState *machine)
     if (kvm_enabled()) {
         pcms->smm = ON_OFF_AUTO_OFF;
     }
+    x86_cpu_compat_set_features("Haswell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
+    x86_cpu_compat_set_features("Haswell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
+    x86_cpu_compat_set_features("Broadwell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
+    x86_cpu_compat_set_features("Broadwell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
 }
 
 static void pc_compat_2_2(MachineState *machine)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 04a8408..76031e0 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1091,7 +1091,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
             CPUID_EXT2_SYSCALL,
         .features[FEAT_8000_0001_ECX] =
-            CPUID_EXT3_LAHF_LM,
+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
         .features[FEAT_7_0_EBX] =
             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
             CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1124,7 +1124,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
             CPUID_EXT2_SYSCALL,
         .features[FEAT_8000_0001_ECX] =
-            CPUID_EXT3_LAHF_LM,
+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
         .features[FEAT_7_0_EBX] =
             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1159,7 +1159,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
             CPUID_EXT2_SYSCALL,
         .features[FEAT_8000_0001_ECX] =
-            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
         .features[FEAT_7_0_EBX] =
             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
             CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1195,7 +1195,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
             CPUID_EXT2_SYSCALL,
         .features[FEAT_8000_0001_ECX] =
-            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
         .features[FEAT_7_0_EBX] =
             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
-- 
2.4.3

Re: [Qemu-devel] [PATCH rebased for-2.4] target-i386: add ABM to Haswell* and Broadwell* CPU models

[Eduardo Habkost]

On Tue, Jul 07, 2015 at 12:42:01PM +0200, Paolo Bonzini wrote:
> ABM is only implemented as a single instruction set by AMD; all AMD
> processors support both instructions or neither. Intel considers POPCNT
> as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
> ABM flag to indicate support for both POPCNT and LZCNT.  It has to be
> added to Haswell and Broadwell because Haswell, by adding LZCNT, has
> completed the ABM.
> 
> Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
> machine types) on an Haswell-EP machine.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  hw/i386/pc_piix.c | 4 ++++
>  hw/i386/pc_q35.c  | 4 ++++
>  target-i386/cpu.c | 8 ++++----
>  3 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 56cdcb9..d9e9987 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -312,6 +312,10 @@ static void pc_compat_2_3(MachineState *machine)
>      if (kvm_enabled()) {
>          pcms->smm = ON_OFF_AUTO_OFF;
>      }
> +    x86_cpu_compat_set_features("Haswell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> +    x86_cpu_compat_set_features("Haswell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> +    x86_cpu_compat_set_features("Broadwell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> +    x86_cpu_compat_set_features("Broadwell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);

x86_cpu_compat_set_features() is not necessary anymore, please use
PC_COMPAT_2_3 to disable ABM.

-- 
Eduardo

Re: [Qemu-devel] [PATCH rebased for-2.4] target-i386: add ABM to Haswell* and Broadwell* CPU models

[Paolo Bonzini]

On 07/07/2015 19:21, Eduardo Habkost wrote:
> On Tue, Jul 07, 2015 at 12:42:01PM +0200, Paolo Bonzini wrote:
>> ABM is only implemented as a single instruction set by AMD; all AMD
>> processors support both instructions or neither. Intel considers POPCNT
>> as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
>> ABM flag to indicate support for both POPCNT and LZCNT.  It has to be
>> added to Haswell and Broadwell because Haswell, by adding LZCNT, has
>> completed the ABM.
>>
>> Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
>> machine types) on an Haswell-EP machine.
>>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>> ---
>>  hw/i386/pc_piix.c | 4 ++++
>>  hw/i386/pc_q35.c  | 4 ++++
>>  target-i386/cpu.c | 8 ++++----
>>  3 files changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
>> index 56cdcb9..d9e9987 100644
>> --- a/hw/i386/pc_piix.c
>> +++ b/hw/i386/pc_piix.c
>> @@ -312,6 +312,10 @@ static void pc_compat_2_3(MachineState *machine)
>>      if (kvm_enabled()) {
>>          pcms->smm = ON_OFF_AUTO_OFF;
>>      }
>> +    x86_cpu_compat_set_features("Haswell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
>> +    x86_cpu_compat_set_features("Haswell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
>> +    x86_cpu_compat_set_features("Broadwell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
>> +    x86_cpu_compat_set_features("Broadwell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> 
> x86_cpu_compat_set_features() is not necessary anymore, please use
> PC_COMPAT_2_3 to disable ABM.

Would this be appropriate for 2.4, or should I just wait for 2.5?

Paolo

Re: [Qemu-devel] [PATCH rebased for-2.4] target-i386: add ABM to Haswell* and Broadwell* CPU models

[Eduardo Habkost]

On Wed, Jul 08, 2015 at 02:10:42PM +0200, Paolo Bonzini wrote:
> 
> 
> On 07/07/2015 19:21, Eduardo Habkost wrote:
> > On Tue, Jul 07, 2015 at 12:42:01PM +0200, Paolo Bonzini wrote:
> >> ABM is only implemented as a single instruction set by AMD; all AMD
> >> processors support both instructions or neither. Intel considers POPCNT
> >> as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
> >> ABM flag to indicate support for both POPCNT and LZCNT.  It has to be
> >> added to Haswell and Broadwell because Haswell, by adding LZCNT, has
> >> completed the ABM.
> >>
> >> Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
> >> machine types) on an Haswell-EP machine.
> >>
> >> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> >> ---
> >>  hw/i386/pc_piix.c | 4 ++++
> >>  hw/i386/pc_q35.c  | 4 ++++
> >>  target-i386/cpu.c | 8 ++++----
> >>  3 files changed, 12 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> >> index 56cdcb9..d9e9987 100644
> >> --- a/hw/i386/pc_piix.c
> >> +++ b/hw/i386/pc_piix.c
> >> @@ -312,6 +312,10 @@ static void pc_compat_2_3(MachineState *machine)
> >>      if (kvm_enabled()) {
> >>          pcms->smm = ON_OFF_AUTO_OFF;
> >>      }
> >> +    x86_cpu_compat_set_features("Haswell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> >> +    x86_cpu_compat_set_features("Haswell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> >> +    x86_cpu_compat_set_features("Broadwell", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> >> +    x86_cpu_compat_set_features("Broadwell-noTSX", FEAT_8000_0001_ECX, 0, CPUID_EXT3_ABM);
> > 
> > x86_cpu_compat_set_features() is not necessary anymore, please use
> > PC_COMPAT_2_3 to disable ABM.
> 
> Would this be appropriate for 2.4, or should I just wait for 2.5?

As it can be easily worked around by using "-cpu <model>,+abm", I don't
think it qualifies as bug fix.

(Sorry, I just noticed you submitted the patch some time ago but it
slipped through the cracks).

-- 
Eduardo

Re: [Qemu-devel] [PATCH rebased for-2.4] target-i386: add ABM to Haswell* and Broadwell* CPU models

[Eduardo Habkost]

On Tue, Jul 07, 2015 at 12:42:01PM +0200, Paolo Bonzini wrote:
> ABM is only implemented as a single instruction set by AMD; all AMD
> processors support both instructions or neither. Intel considers POPCNT
> as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
> ABM flag to indicate support for both POPCNT and LZCNT.  It has to be
> added to Haswell and Broadwell because Haswell, by adding LZCNT, has
> completed the ABM.
> 
> Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
> machine types) on an Haswell-EP machine.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

For future reference: ABM was added to the KVM kernel code by commit
v2.6.31-rc1~393^2~30. Some features required to run Haswell and
Broadwell (FMA, BMI1, AVX2, BMI2) were added much later, at
v3.3-rc1~131^2~33.

Thus, any host that can run the Haswell and Broadwell CPU models today
should be able to run them with ABM enabled, and this patch doesn't
introduce any runnability changes in the existing CPU models.

-- 
Eduardo