Re: [Qemu-devel] [PATCH v4 3/4] target-arm: Extend the gic node properties

[Claudio Fontana <claudio.fontana@huawei.com>]

Hello Christoffer,

just one question:

> In preparation for adding the GICv2m which requires address specifiers
> and is a subnode of the gic, we extend the gic DT definition to specify
> the #address-cells and #size-cells properties and add an empty ranges
> property properties of the DT node, since this is required to add the
> v2m node as a child of the gic node.
>
> Note that we must also expand the irq-map to reference the gic with the
> right address-cells as a consequence of this change.
>
> Reviewed-by: Eric Auger <address@hidden>
> Suggested-by: Shanker Donthineni <address@hidden>
> Signed-off-by: Christoffer Dall <address@hidden>
> ---
> Changes since v3:
>  - Rewrote patch and changed authorship and tags accordingly
>  - Fixed spelling in commit message
> Changes since v2:
>  - New separate patch factoring out changes to existing code for eased
>    bisectability in case we broke something
>  - The above fixes the issue with non-MSI compatible guests.
>
>  hw/arm/virt.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index e5235ef..387dac8 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -317,6 +317,9 @@ static void fdt_add_gic_node(VirtBoardInfo *vbi)
>                                       2, vbi->memmap[VIRT_GIC_DIST].size,
>                                       2, vbi->memmap[VIRT_GIC_CPU].base,
>                                       2, vbi->memmap[VIRT_GIC_CPU].size);
> +    qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2);
> +    qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2);
> +    qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0);
>      qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle);
>  }
>  
> @@ -585,7 +588,7 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, 
> uint32_t gic_phandle,
>                                  int first_irq, const char *nodename)
>  {
>      int devfn, pin;
> -    uint32_t full_irq_map[4 * 4 * 8] = { 0 };
> +    uint32_t full_irq_map[4 * 4 * 10] = { 0 };
>      uint32_t *irq_map = full_irq_map;
>  
>      for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
> @@ -598,13 +601,13 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, 
> uint32_t gic_phandle,
>              uint32_t map[] = {
>                  devfn << 8, 0, 0,                           /* devfn */
>                  pin + 1,                                    /* PCI pin */
> -                gic_phandle, irq_type, irq_nr, irq_level }; /* GIC irq */
> +                gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */

can you help me understand how to decode this?
We are adding two 32bit "0" values in the map.
So now gic_phandle field occupies a total of 3 x 32bit values.
Is this really what was intended?

If the #address-cell and #size-cells of the intc are 2 and 2 respectively,
shouldn't this be

gic_phandle, 0, irq_type, irq_nr, irq_level ?

Too much time since I read this code I guess..

Thanks!

CLaudio

>  
>              /* Convert map to big endian */
> -            for (i = 0; i < 8; i++) {
> +            for (i = 0; i < 10; i++) {
>                  irq_map[i] = cpu_to_be32(map[i]);
>              }
> -            irq_map += 8;
> +            irq_map += 10;
>          }
>      }
>  
> -- 
> 2.1.2.330.g565301e.dirty
>