From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZDDN3-00057e-EW for qemu-devel@nongnu.org; Thu, 09 Jul 2015 11:04:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZDDMx-000620-NU for qemu-devel@nongnu.org; Thu, 09 Jul 2015 11:04:17 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57226) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZDDMx-00061s-Ho for qemu-devel@nongnu.org; Thu, 09 Jul 2015 11:04:11 -0400 References: <1436412413-27389-1-git-send-email-crosthwaite.peter@gmail.com> From: Paolo Bonzini Message-ID: <559E8D68.7000703@redhat.com> Date: Thu, 9 Jul 2015 17:04:08 +0200 MIME-Version: 1.0 In-Reply-To: <1436412413-27389-1-git-send-email-crosthwaite.peter@gmail.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] cpu_defs: Simplify CPUTLB padding logic List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite , qemu-devel@nongnu.org Cc: Peter Crosthwaite , rth@twiddle.net On 09/07/2015 05:26, Peter Crosthwaite wrote: > There was a complicated subtractive arithmetic for determining the > padding on the CPUTLBEntry structure. Simplify this with a union. > > Signed-off-by: Peter Crosthwaite > --- > Changed since v1: > Remove un-needed anonymous union (Paolo review) > --- > include/exec/cpu-defs.h | 21 ++++++++++----------- > 1 file changed, 10 insertions(+), 11 deletions(-) > > diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h > index 98b9cff..c6828cc 100644 > --- a/include/exec/cpu-defs.h > +++ b/include/exec/cpu-defs.h > @@ -98,24 +98,23 @@ typedef uint64_t target_ulong; > > #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) > > -typedef struct CPUTLBEntry { > +typedef union CPUTLBEntry { > /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address > bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not > go directly to ram. > bit 3 : indicates that the entry is invalid > bit 2..0 : zero > */ > - target_ulong addr_read; > - target_ulong addr_write; > - target_ulong addr_code; > - /* Addend to virtual address to get host address. IO accesses > - use the corresponding iotlb value. */ > - uintptr_t addend; > + struct { > + target_ulong addr_read; > + target_ulong addr_write; > + target_ulong addr_code; > + /* Addend to virtual address to get host address. IO accesses > + use the corresponding iotlb value. */ > + uintptr_t addend; > + }; > /* padding to get a power of two size */ > - uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - > - (sizeof(target_ulong) * 3 + > - ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + > - sizeof(uintptr_t))]; > + uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; > } CPUTLBEntry; > > QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); > Thanks, queued for 2.5. Paolo