From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZF2uA-0000qd-SW for qemu-devel@nongnu.org; Tue, 14 Jul 2015 12:18:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZF2u6-0003tn-OD for qemu-devel@nongnu.org; Tue, 14 Jul 2015 12:18:02 -0400 Received: from mail-wi0-x233.google.com ([2a00:1450:400c:c05::233]:38136) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZF2u6-0003t6-Gm for qemu-devel@nongnu.org; Tue, 14 Jul 2015 12:17:58 -0400 Received: by wicmv11 with SMTP id mv11so18722721wic.1 for ; Tue, 14 Jul 2015 09:17:57 -0700 (PDT) Sender: Paolo Bonzini References: <1436888717-8122-1-git-send-email-aurelien@aurel32.net> <1436888717-8122-3-git-send-email-aurelien@aurel32.net> From: Paolo Bonzini Message-ID: <55A53633.1050106@redhat.com> Date: Tue, 14 Jul 2015 18:17:55 +0200 MIME-Version: 1.0 In-Reply-To: <1436888717-8122-3-git-send-email-aurelien@aurel32.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , qemu-devel@nongnu.org Cc: =?UTF-8?Q?Herv=c3=a9_Poussineau?= , Leon Alrae On 14/07/2015 17:45, Aurelien Jarno wrote: > The LWL/LDL instructions mask the GPR with a mask depending on the > address alignement. It is currently computed by doing: > > mask = 0x7fffffffffffffffull >> (t1 ^ 63) > > It's simpler to generate it by doing: > > mask = (1 << t1) - 1 Using ~(-1 << t1) may let you use an ANDN instruction, and is also the same number of instructions on x86. Paolo > It uses the same number of TCG instructions, but it avoids a 32/64-bit > constant loading which can take a few instructions on RISC hosts. > > Cc: Leon Alrae > Tested-by: Hervé Poussineau > Signed-off-by: Aurelien Jarno > --- > target-mips/translate.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 0ac3bd8..9891209 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -2153,9 +2153,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, > tcg_gen_andi_tl(t0, t0, ~7); > tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); > tcg_gen_shl_tl(t0, t0, t1); > - tcg_gen_xori_tl(t1, t1, 63); > - t2 = tcg_const_tl(0x7fffffffffffffffull); > - tcg_gen_shr_tl(t2, t2, t1); > + t2 = tcg_const_tl(1); > + tcg_gen_shl_tl(t2, t2, t1); > + tcg_gen_subi_tl(t2, t2, 1); > gen_load_gpr(t1, rt); > tcg_gen_and_tl(t1, t1, t2); > tcg_temp_free(t2); > @@ -2246,9 +2246,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, > tcg_gen_andi_tl(t0, t0, ~3); > tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); > tcg_gen_shl_tl(t0, t0, t1); > - tcg_gen_xori_tl(t1, t1, 31); > - t2 = tcg_const_tl(0x7fffffffull); > - tcg_gen_shr_tl(t2, t2, t1); > + t2 = tcg_const_tl(1); > + tcg_gen_shl_tl(t2, t2, t1); > + tcg_gen_subi_tl(t2, t2, 1); > gen_load_gpr(t1, rt); > tcg_gen_and_tl(t1, t1, t2); > tcg_temp_free(t2); >