From: Paolo Bonzini <pbonzini@redhat.com>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: "Leon Alrae" <leon.alrae@imgtec.com>,
"Hervé Poussineau" <hpoussin@reactos.org>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation
Date: Tue, 14 Jul 2015 19:11:50 +0200 [thread overview]
Message-ID: <55A542D6.1030501@redhat.com> (raw)
In-Reply-To: <20150714164503.GB7569@aurel32.net>
On 14/07/2015 18:45, Aurelien Jarno wrote:
>>> > >
>>> > > mask = 0x7fffffffffffffffull >> (t1 ^ 63)
>>> > >
>>> > > It's simpler to generate it by doing:
>>> > >
>>> > > mask = (1 << t1) - 1
>> >
>> > Using ~(-1 << t1) may let you use an ANDN instruction, and is also the
>> > same number of instructions on x86.
>> >
> Indeed thanks for the hint. The generated code has the same size, but is
> one instruction less:
>
> mov 0x88(%rsp),%r10
> shlx %r10,%rbx,%rbx
> - mov $0x1,%r11d
> + mov $0xffffffffffffffff,%r11
> shlx %r10,%r11,%r11
> - dec %r11
> mov 0x18(%r14),%r10
> - and %r11,%r10
> + andn %r10,%r11,%r10
> or %r10,%rbx
> movslq %ebx,%rbx
Oh, indeed I forgot about the fancy new x86 bit manipulation
instructions! Even better. :)
Paolo
prev parent reply other threads:[~2015-07-14 17:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-14 15:45 [Qemu-devel] [PATCH 0/2] target-mips: fix Windows NT support Aurelien Jarno
2015-07-14 15:45 ` [Qemu-devel] [PATCH for-2.4 1/2] target-mips: fix page fault address for LWL/LWR/LDL/LDR Aurelien Jarno
2015-07-15 16:30 ` Leon Alrae
2015-07-14 15:45 ` [Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation Aurelien Jarno
2015-07-14 16:17 ` Paolo Bonzini
2015-07-14 16:45 ` Aurelien Jarno
2015-07-14 17:11 ` Paolo Bonzini [this message]
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