Re: [Qemu-devel] [PATCH] target-mips: apply workaround for TCG optimizations for MFC1

[Richard Henderson <rth@twiddle.net>]

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On 07/15/2015 09:06 AM, Aurelien Jarno wrote:
> On 2015-07-15 09:31, Paolo Bonzini wrote:
>> Ok, I see your point.  If you put it like this :) the fault definitely
>> lies in the backends.  What I'm proposing would be in a new
>> tcg_reg_alloc_trunc function, and it would require implementing a
>> non-noop trunc.
>
> Why not reusing the existing trunc_shr_i64_i32 op? AFAIU, it has been
> designed exactly for that.

Indeed.

> Actually I think we should implement the following ops as optional but
> *real* TCG ops:
> - trunc_shr_i64_i32
> - extu_i32_i64
> - ext_i32_i64

While we could perhaps gain something from the last two, reliably using the 
first is probably the most important.

I've been unable to reproduce the binary in question.  I'm curious if something 
as simple as this helps.  Alternately, the two hunks might just cancel each 
other out and result in no change.


r~

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diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 45098c3..cc223c1 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1751,17 +1751,17 @@ void tcg_gen_trunc_shr_i64_i32(TCGv_i32 ret, TCGv_i64 arg, unsigned count)
             tcg_gen_mov_i32(ret, TCGV_LOW(t));
             tcg_temp_free_i64(t);
         }
-    } else if (TCG_TARGET_HAS_trunc_shr_i32) {
-        tcg_gen_op3i_i32(INDEX_op_trunc_shr_i32, ret,
-                         MAKE_TCGV_I32(GET_TCGV_I64(arg)), count);
-    } else if (count == 0) {
-        tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
-    } else {
+        return;
+    }
+    if (!TCG_TARGET_HAS_trunc_shr_i32 && count != 0) {
         TCGv_i64 t = tcg_temp_new_i64();
         tcg_gen_shri_i64(t, arg, count);
-        tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(t)));
         tcg_temp_free_i64(t);
+        arg = t;
+        count = 0;
     }
+    tcg_gen_op3i_i32(INDEX_op_trunc_shr_i32, ret,
+                     MAKE_TCGV_I32(GET_TCGV_I64(arg)), count);
 }
 
 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 7e088b1..334d4c3 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2374,6 +2374,13 @@ static inline int tcg_gen_code_common(TCGContext *s,
             tcg_reg_alloc_call(s, op->callo, op->calli, args,
                                dead_args, sync_args);
             break;
+        case INDEX_op_trunc_shr_i32:
+            if (!TCG_TARGET_HAS_trunc_shr_i32) {
+                tcg_assert(args[2] == 0);
+                tcg_reg_alloc_mov(s, def, args, dead_args, sync_args);
+                break;
+            }
+            /* FALLTHRU */
         default:
             /* Sanity check that we've not introduced any unhandled opcodes. */
             if (def->flags & TCG_OPF_NOT_PRESENT) {