From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38153) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFKus-0000t2-5w for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:31:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFKuo-0001eY-VH for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:31:58 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52645) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFKuo-0001eO-Pi for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:31:54 -0400 References: <1436891912-14742-1-git-send-email-leon.alrae@imgtec.com> <20150714170928.GC7569@aurel32.net> <55A552F1.70000@redhat.com> <20150714183735.GA2685@aurel32.net> <55A57792.5070509@redhat.com> <20150714220938.GA11278@aurel32.net> <55A60C4C.3070406@redhat.com> <20150715080633.GJ11361@aurel32.net> <55A62FAE.7030806@twiddle.net> <20150715101447.GD20210@aurel32.net> From: Paolo Bonzini Message-ID: <55A644A3.1080004@redhat.com> Date: Wed, 15 Jul 2015 13:31:47 +0200 MIME-Version: 1.0 In-Reply-To: <20150715101447.GD20210@aurel32.net> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-mips: apply workaround for TCG optimizations for MFC1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , Richard Henderson Cc: Leon Alrae , qemu-devel@nongnu.org On 15/07/2015 12:14, Aurelien Jarno wrote: > I think for 2.4 we should go with the ADDR32 way, using the following > kind of patch. It works when %gs is in use, but has to be extended when > it's not in use. The idea is that qemu_ld/st should behave like other > 32-bit ops, that is ignore the high part of the register. > > diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c > index ff4d9cf..e139c44 100644 > --- a/tcg/i386/tcg-target.c > +++ b/tcg/i386/tcg-target.c > @@ -1572,6 +1572,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) > if (GUEST_BASE && guest_base_flags) { > seg = guest_base_flags; > offset = 0; > + if (TARGET_LONG_BITS == 32) { > + seg = P_ADDR32; > + } > } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) { > tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE); > tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); > @@ -1705,6 +1708,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) > if (GUEST_BASE && guest_base_flags) { > seg = guest_base_flags; > offset = 0; > + if (TARGET_LONG_BITS == 32) { > + seg = P_ADDR32; > + } > } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) { > tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE); > tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); > > Yup, I'll post the aarch64 changes too. Paolo