From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40299) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFqjA-0005OJ-Ge for qemu-devel@nongnu.org; Thu, 16 Jul 2015 17:30:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFqj7-0005pj-BA for qemu-devel@nongnu.org; Thu, 16 Jul 2015 17:30:00 -0400 Received: from mail-wg0-x22d.google.com ([2a00:1450:400c:c00::22d]:33517) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFqj7-0005pf-5D for qemu-devel@nongnu.org; Thu, 16 Jul 2015 17:29:57 -0400 Received: by wgmn9 with SMTP id n9so68303952wgm.0 for ; Thu, 16 Jul 2015 14:29:56 -0700 (PDT) Sender: Richard Henderson References: <20150715205423.GA23115@aurel32.net> From: Richard Henderson Message-ID: <55A82251.6020308@twiddle.net> Date: Thu, 16 Jul 2015 22:29:53 +0100 MIME-Version: 1.0 In-Reply-To: <20150715205423.GA23115@aurel32.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 00/13] tcg/sparc v8plus code generation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: Paolo Bonzini , qemu-devel@nongnu.org On 07/15/2015 09:54 PM, Aurelien Jarno wrote: > While I understand why we need the new trunc_shr_i32 opcode for MIPS64 > (the 32-bit values must be kept sign-extended), I currently fail to > see why it is needed for SPARC. As far as I recall, it improves code for extracting high parts of 64-bit quantities. Without this, we wind up with a 64-bit shift, requiring a 64-bit temp register, followed by the "real" truncate which can copy the data to a 32-bit destination register. r~