From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZGnCu-0002YV-3X for qemu-devel@nongnu.org; Sun, 19 Jul 2015 07:56:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZGnCt-0001zh-8K for qemu-devel@nongnu.org; Sun, 19 Jul 2015 07:56:36 -0400 Sender: Paolo Bonzini References: <1437258018-13982-1-git-send-email-benh@kernel.crashing.org> <1437258018-13982-3-git-send-email-benh@kernel.crashing.org> From: Paolo Bonzini Message-ID: <55AB9068.8050202@redhat.com> Date: Sun, 19 Jul 2015 13:56:24 +0200 MIME-Version: 1.0 In-Reply-To: <1437258018-13982-3-git-send-email-benh@kernel.crashing.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 3/4] ppc: Use split I/D mmu modes to avoid flushes on interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org On 19/07/2015 00:20, Benjamin Herrenschmidt wrote: > + * For BookE, we need in theory 8 MMU modes, which would > + * reduce performance, so instead, we ignore msr_hv and > + * will flush on HV context switches. We *could* improve > + * things a bit if needed by using 4 and 5 as HV and flush > + * only when HV mode changes AS but that complicates things > + * as we would need to remember which is the current AS mode > + * for HV for I and D and split more would be hell. > + * 8 MMU modes wouldn't reduce performance, only 9 would: #define CPU_TLB_BITS \ MIN(8, \ TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ (NB_MMU_MODES <= 1 ? 0 : \ NB_MMU_MODES <= 2 ? 1 : \ NB_MMU_MODES <= 4 ? 2 : \ NB_MMU_MODES <= 8 ? 3 : 4)) Paolo