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From: Richard Henderson <rth@twiddle.net>
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Date: Tue, 21 Jul 2015 07:39:50 +0100
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Subject: Re: [Qemu-devel] [PATCH v3] tcg/ppc: Improve unaligned load/store
 handling on 64-bit backend
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To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>, Alexander Graf <agraf@suse.de>

On 07/21/2015 07:33 AM, Benjamin Herrenschmidt wrote:
> On Tue, 2015-07-21 at 07:27 +0100, Richard Henderson wrote:
>> On 07/21/2015 06:19 AM, Benjamin Herrenschmidt wrote:
>>> +    /* Clear the non-page, non-alignment bits from the address */
>>>        if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
>>> +        /* We don't support unaligned accesses on 32-bits, preserve
>>> +         * the bottom bits and thus trigger a comparison failure on
>>> +         * unaligned accesses
>>> +         */
>>>            tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
>>>                        (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
>>
>> Why don't you support this unaligned acess with 32-bit guests?
>
> No reason, I just didn't get to do it yet. It's possible, I was just
> lazy :-) It also adds one instruction. On 64-bit we always have 2
> instructions anyway so it wasn't adding any overhead really, on 32-bit
> we get away with a single rlwinm, while adding the unaligned support
> would make it an addi + rlwinm.

Ah, ok.  I wondered if some older 32-bit host ppc didn't allow it, and the 
32-bit guest paid the price.  Anyway,

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~