From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZHWHc-0000r8-Jn for qemu-devel@nongnu.org; Tue, 21 Jul 2015 08:04:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZHWHX-0003vS-IZ for qemu-devel@nongnu.org; Tue, 21 Jul 2015 08:04:28 -0400 Message-ID: <55AE3542.5080300@suse.de> Date: Tue, 21 Jul 2015 14:04:18 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1437455978.5809.2.camel@kernel.crashing.org> <55ADE64A.7050702@twiddle.net> <1437460396.5809.5.camel@kernel.crashing.org> <55ADE936.8090407@twiddle.net> <1437471990.5809.7.camel@kernel.crashing.org> In-Reply-To: <1437471990.5809.7.camel@kernel.crashing.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3] tcg/ppc: Improve unaligned load/store handling on 64-bit backend List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt , Richard Henderson Cc: Paolo Bonzini , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Aurelien Jarno On 07/21/15 11:46, Benjamin Herrenschmidt wrote: > On Tue, 2015-07-21 at 07:39 +0100, Richard Henderson wrote: >> On 07/21/2015 07:33 AM, Benjamin Herrenschmidt wrote: >>> On Tue, 2015-07-21 at 07:27 +0100, Richard Henderson wrote: >>>> On 07/21/2015 06:19 AM, Benjamin Herrenschmidt wrote: >>>>> + /* Clear the non-page, non-alignment bits from the address */ >>>>> if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) { >>>>> + /* We don't support unaligned accesses on 32-bits, preserve >>>>> + * the bottom bits and thus trigger a comparison failure on >>>>> + * unaligned accesses >>>>> + */ >>>>> tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, >>>>> (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS); >>>> Why don't you support this unaligned acess with 32-bit guests? >>> No reason, I just didn't get to do it yet. It's possible, I was just >>> lazy :-) It also adds one instruction. On 64-bit we always have 2 >>> instructions anyway so it wasn't adding any overhead really, on 32-bit >>> we get away with a single rlwinm, while adding the unaligned support >>> would make it an addi + rlwinm. >> Ah, ok. I wondered if some older 32-bit host ppc didn't allow it, and the >> 32-bit guest paid the price. Anyway, > No, most implementations support unaligned accesses in common cases. I > think the worst embedded variants might trap when crossing page > boundaries but that's about it. I don't think we bother emulating > this though. > >> Reviewed-by: Richard Henderson > Thanks. So who can pick those up? PPC TCG is pretty much unmaintained since Malc disappeared, no? Alex