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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Mon, 27 Jul 2015 10:46:12 +0200
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Subject: Re: [Qemu-devel] BIOS regression since v2.3.0 (misaligned longword
 i/o to address 0xffff)
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To: Stefan Weil <sw@weilnetz.de>, QEMU Developer <qemu-devel@nongnu.org>, Gerd Hoffmann <kraxel@redhat.com>



On 27/07/2015 08:36, Stefan Weil wrote:
> commit 457ba42878bd9f704e5a6c1c7bc7fcced686fe4e
> Author: Paolo Bonzini <pbonzini@redhat.com>
> Date:   Thu May 15 13:22:28 2014 +0200
> 
>     smm: complete SMM setup
> 
>     SMI generation requires two bits to be set in PIIX4, one for APMC
>     interrupts specifically and a general one.
> 
>     For Q35 it is the same, plus it is a good thing to lock SMIs after
>     enabling them.
> 
>     Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> 
> :040000 040000 5bfd5601430bc5263ac0a6f8a15a131f3bc8678e
> 5e0901b1c5ae4c79ed4c34c8bd27e7daf9006086 M    src
> 

Is this enough to fix it?

--- a/src/fw/smm.c
+++ b/src/fw/smm.c
@@ -184,7 +184,7 @@ static void piix4_apmc_smm_setup(int isabdf, int i440_bdf)
 
     /* enable SMI generation */
     value = inl(acpi_pm_base + PIIX_PMIO_GLBCTL);
-    outl(acpi_pm_base + PIIX_PMIO_GLBCTL, value | PIIX_PMIO_GLBCTL_SMI_EN);
+    outl(value | PIIX_PMIO_GLBCTL_SMI_EN, acpi_pm_base + PIIX_PMIO_GLBCTL);
 
     smm_relocate_and_restore();
 

Paolo