From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:45566)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <sw@weilnetz.de>) id 1ZJely-0000cT-58
	for qemu-devel@nongnu.org; Mon, 27 Jul 2015 05:32:38 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <sw@weilnetz.de>) id 1ZJelt-0005q9-5m
	for qemu-devel@nongnu.org; Mon, 27 Jul 2015 05:32:38 -0400
Received: from smtp.mail.uni-mannheim.de ([134.155.96.80]:48472)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <sw@weilnetz.de>) id 1ZJels-0005pn-Vs
	for qemu-devel@nongnu.org; Mon, 27 Jul 2015 05:32:33 -0400
References: <55B535BE.60806@weilnetz.de> <55B5C669.8090702@weilnetz.de>
	<55B5CE9B.50008@weilnetz.de> <55B5D172.3060003@weilnetz.de>
	<55B5EFD4.5030105@redhat.com>
From: Stefan Weil <sw@weilnetz.de>
Message-ID: <55B5FA9D.8070803@weilnetz.de>
Date: Mon, 27 Jul 2015 11:32:13 +0200
MIME-Version: 1.0
In-Reply-To: <55B5EFD4.5030105@redhat.com>
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] BIOS regression since v2.3.0 (misaligned longword
 i/o to address 0xffff)
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Paolo Bonzini <pbonzini@redhat.com>, QEMU Developer <qemu-devel@nongnu.org>, Gerd Hoffmann <kraxel@redhat.com>

Am 27.07.2015 um 10:46 schrieb Paolo Bonzini:
> On 27/07/2015 08:36, Stefan Weil wrote:
>> commit 457ba42878bd9f704e5a6c1c7bc7fcced686fe4e
>> Author: Paolo Bonzini <pbonzini@redhat.com>
>> Date:   Thu May 15 13:22:28 2014 +0200
>>
>>     smm: complete SMM setup
>>
>>     SMI generation requires two bits to be set in PIIX4, one for APMC
>>     interrupts specifically and a general one.
>>
>>     For Q35 it is the same, plus it is a good thing to lock SMIs after
>>     enabling them.
>>
>>     Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>>
>> :040000 040000 5bfd5601430bc5263ac0a6f8a15a131f3bc8678e
>> 5e0901b1c5ae4c79ed4c34c8bd27e7daf9006086 M    src
> Is this enough to fix it?
>
> --- a/src/fw/smm.c
> +++ b/src/fw/smm.c
> @@ -184,7 +184,7 @@ static void piix4_apmc_smm_setup(int isabdf, int i440_bdf)
>  
>      /* enable SMI generation */
>      value = inl(acpi_pm_base + PIIX_PMIO_GLBCTL);
> -    outl(acpi_pm_base + PIIX_PMIO_GLBCTL, value | PIIX_PMIO_GLBCTL_SMI_EN);
> +    outl(value | PIIX_PMIO_GLBCTL_SMI_EN, acpi_pm_base + PIIX_PMIO_GLBCTL);
>  
>      smm_relocate_and_restore();
>  
>
> Paolo


Yes, and the new code also looks much better for an outl function call. :-)
You may add

Reviewed-by: Stefan Weil <sw@weilnetz.de>

Stefan