From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMImw-0003HW-0Y for qemu-devel@nongnu.org; Mon, 03 Aug 2015 12:40:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZMImp-0006OM-Ns for qemu-devel@nongnu.org; Mon, 03 Aug 2015 12:40:33 -0400 Received: from mail-pa0-x233.google.com ([2607:f8b0:400e:c03::233]:34695) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMImp-0006Ls-G6 for qemu-devel@nongnu.org; Mon, 03 Aug 2015 12:40:27 -0400 Received: by pawu10 with SMTP id u10so16516052paw.1 for ; Mon, 03 Aug 2015 09:40:24 -0700 (PDT) Sender: Richard Henderson References: From: Richard Henderson Message-ID: <55BF9975.7020002@twiddle.net> Date: Mon, 3 Aug 2015 09:40:21 -0700 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Consult] tilegx: About floating point instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Chen Gang , Chris Metcalf , Peter Maydell , =?UTF-8?Q?Andreas_F=c3=a4rber?= , "walt@tilera.com" Cc: qemu-devel On 08/01/2015 02:47 AM, Chen Gang wrote: > I am just adding floating point instructions (e.g. fsingle_add1), but > for me, I can not find any details about them (the ISA documents only > give a summary description, but not details), e.g. The tilegx splits the four/six cycle arithmetic into multiple black-box instructions. You need only really implement one of the four, with the rest of them being implemented as nops or moves. Looking at what gcc produces gives the hints: fdouble_unpack_min min, srca, srcb fdouble_unpack_max max, srca, srcb fdouble_add_flags flg, srca, srcb fdouble_addsub max, min, flg fdouble_pack1 dst, max, flg fdouble_pack2 dst, max, zero The unpack, addsub, and pack2 insns can be ignored, the add_flags insn can perform the whole operation, the pack1 insn performs a move from "flg" to "dst". Similarly for the single-precision: fsingle_add1 tmp, srca, srcb fsingle_addsub2 tmp, srca, srcb fsingle_pack1 flg, tmp fsingle_pack2 dst, tmp, flg The add1 insn performs the whole operation, the addsub2 and pack1 insns are ignored, and the pack2 insn is a move from tmp to dst. r~