From: Paolo Bonzini <pbonzini@redhat.com>
To: Alvise Rigo <a.rigo@virtualopensystems.com>,
qemu-devel@nongnu.org, mttcg@listserver.greensocs.com
Cc: claudio.fontana@huawei.com, jani.kokkonen@huawei.com,
tech@virtualopensystems.com, alex.bennee@linaro.org
Subject: Re: [Qemu-devel] [RFC v4 1/9] exec.c: Add new exclusive bitmap to ram_list
Date: Tue, 11 Aug 2015 15:52:41 +0200 [thread overview]
Message-ID: <55C9FE29.2080204@redhat.com> (raw)
In-Reply-To: <1438966995-5913-2-git-send-email-a.rigo@virtualopensystems.com>
On 07/08/2015 19:03, Alvise Rigo wrote:
> +static inline int cpu_physical_memory_excl_atleast_one_clean(ram_addr_t addr)
> +{
> + unsigned long *bitmap = ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE];
> + unsigned long next, end;
> +
> + if (likely(smp_cpus <= BITS_PER_LONG)) {
This only works if smp_cpus divides BITS_PER_LONG, i.e. BITS_PER_LONG %
smp_cpus == 0.
> + unsigned long mask = (1 << smp_cpus) - 1;
> +
> + return
> + (mask & (bitmap[BIT_WORD(EXCL_BITMAP_GET_OFFSET(addr))] >>
> + (EXCL_BITMAP_GET_OFFSET(addr) & (BITS_PER_LONG-1)))) != mask;
> + }
> +
> + end = BIT_WORD(EXCL_BITMAP_GET_OFFSET(addr)) + smp_cpus;
> + next = find_next_zero_bit(bitmap, end,
> + BIT_WORD(EXCL_BITMAP_GET_OFFSET(addr)));
> +
> + return next < end;
> +static inline int cpu_physical_memory_excl_is_dirty(ram_addr_t addr,
> + unsigned long cpu)
> +{
> + unsigned long *bitmap = ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE];
> + unsigned long end, next;
> + uint32_t add;
> +
> + assert(cpu <= smp_cpus);
> +
> + if (likely(smp_cpus <= BITS_PER_LONG)) {
> + cpu = (cpu == smp_cpus) ? (1 << cpu) - 1 : (1 << cpu);
> +
> + return cpu & (bitmap[BIT_WORD(EXCL_BITMAP_GET_OFFSET(addr))] >>
> + (EXCL_BITMAP_GET_OFFSET(addr) & (BITS_PER_LONG-1)));
> + }
> +
> + add = (cpu == smp_cpus) ? 0 : 1;
Why not have a separate function for the cpu == smp_cpus case?
I don't think real hardware has ll/sc per CPU. Can we have the bitmap as:
- 0 if one or more CPUs have the address set to exclusive, _and_ no CPU
has done a concurrent access
- 1 if no CPUs have the address set to exclusive, _or_ one CPU has done
a concurrent access.
Then:
- ll sets the bit to 0, and requests a flush if it was 1
- when setting a TLB entry, set it to TLB_EXCL if the bitmap has 0
- in the TLB_EXCL slow path, set the bit to 1 and, for conditional
stores, succeed if the bit was 0
- when removing an exclusive entry, set the bit to 1
Paolo
next prev parent reply other threads:[~2015-08-11 13:52 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-07 17:03 [Qemu-devel] [RFC v4 0/9] Slow-path for atomic instruction translation Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 1/9] exec.c: Add new exclusive bitmap to ram_list Alvise Rigo
2015-08-11 13:52 ` Paolo Bonzini [this message]
2015-08-11 14:24 ` Peter Maydell
2015-08-11 14:34 ` alvise rigo
2015-08-11 15:54 ` alvise rigo
2015-08-11 15:55 ` Paolo Bonzini
2015-08-11 16:11 ` alvise rigo
2015-08-11 16:32 ` Paolo Bonzini
2015-08-12 7:31 ` alvise rigo
2015-08-12 12:36 ` Paolo Bonzini
2015-08-12 13:02 ` Peter Maydell
2015-08-12 14:04 ` alvise rigo
2015-08-12 14:10 ` Paolo Bonzini
2015-08-12 14:32 ` alvise rigo
2015-09-10 13:04 ` alvise rigo
2015-09-10 16:19 ` Alex Bennée
2015-09-10 17:36 ` alvise rigo
2015-09-10 16:25 ` Paolo Bonzini
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 2/9] softmmu: Add new TLB_EXCL flag Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 3/9] softmmu: Add helpers for a new slowpath Alvise Rigo
2015-08-11 13:32 ` alvise rigo
2015-08-11 13:52 ` Paolo Bonzini
2015-08-11 15:55 ` alvise rigo
2015-08-12 12:43 ` Paolo Bonzini
2015-08-12 13:09 ` alvise rigo
2015-08-12 13:14 ` Paolo Bonzini
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 4/9] tcg-op: create new TCG qemu_{ld, st} excl variants Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 5/9] configure: Enable/disable new qemu_{ld, st} excl insns Alvise Rigo
2015-08-08 12:44 ` Aurelien Jarno
2015-08-08 13:57 ` Peter Maydell
2015-08-09 8:11 ` Alex Bennée
2015-08-09 8:40 ` Aurelien Jarno
2015-08-09 9:51 ` Alex Bennée
2015-08-09 10:13 ` Aurelien Jarno
2015-08-09 16:27 ` Alex Bennée
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 6/9] tcg-i386: Implement excl variants of qemu_{ld, st} Alvise Rigo
2015-08-08 13:00 ` Aurelien Jarno
2015-08-10 7:50 ` alvise rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 7/9] tcg-arm: " Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 8/9] tcg-aarch64: " Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 9/9] target-arm: translate: Use ld/st excl for atomic insns Alvise Rigo
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