From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57747) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZU5dc-0005Ax-5c for qemu-devel@nongnu.org; Tue, 25 Aug 2015 00:15:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZU5dY-0007qh-5b for qemu-devel@nongnu.org; Tue, 25 Aug 2015 00:15:08 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:33161) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZU5dX-0007pm-Tz for qemu-devel@nongnu.org; Tue, 25 Aug 2015 00:15:04 -0400 Received: by pacti10 with SMTP id ti10so39881899pac.0 for ; Mon, 24 Aug 2015 21:15:02 -0700 (PDT) Sender: Richard Henderson References: <1440433079-14458-1-git-send-email-rth@twiddle.net> <1440433079-14458-31-git-send-email-rth@twiddle.net> From: Richard Henderson Message-ID: <55DBEBC4.4030805@twiddle.net> Date: Mon, 24 Aug 2015 21:15:00 -0700 MIME-Version: 1.0 In-Reply-To: <1440433079-14458-31-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: walt@tilera.com, cmetcalf@ezchip.com, xili_gchen_5257@hotmail.com, peter.maydell@linaro.org On 08/24/2015 09:17 AM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target-tilegx/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 49 insertions(+), 1 deletion(-) > > diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c > index 210e912..2a0798a 100644 > --- a/target-tilegx/translate.c > +++ b/target-tilegx/translate.c > @@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb, > tcg_temp_free(t0); > } > > +static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca, > + unsigned srcb, TileExcp excp) > +{ > +#ifdef CONFIG_USER_ONLY > + TCGv_i32 t = tcg_const_i32((dest << 16) | (srca << 8) | srcb); > + tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam)); > + tcg_temp_free_i32(t); > + gen_exception(dc, excp); > +#else > + gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED); > +#endif > +} This is broken. While it does work well enough for Hello World, implementing a non-trap instruction with an exception is extremely dicey for TileGX. The issue is that TileGX bundles operate atomically, with no RAW issues between the instructions of the bundle. Consider a bundle like { add r0, r0, r1 ; exch r2, r0, r3 } In Chen's implementation, the writeback to r0 would occur before the exception, and so the exch would happen to the wrong address. In my implementation here, the exception would occur before the writeback, and so the result of the add would be discarded. While retaining the current start_exclusive scheme, it would appear that we need to store more data here -- to wit, the contents of the registers not their numbers -- and delay the exception until after writeback. Even better, of course, would be to not exit the TB at all, and use host atomic instructions... I suppose that multi-threading patch set is still in limbo? r~