Re: [Qemu-devel] [PATCH] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Leon Alrae <leon.alrae@imgtec.com>]

On 18/08/2015 18:35, Petar Jovanovic wrote:
> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
> 
> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> they require any particular mode for its FPU. This patch removes the checks
> that may break a program that uses these instructions.

This seems to be correct starting from MIPS32R2, but I'm not sure about older
cores. Do we really want to remove the restrictions for them as well?

> @@ -9839,7 +9837,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
>          opn = "movn.d";
>          break;
>      case OPC_RECIP_D:
> -        check_cp1_64bitmode(ctx);

I think this needs check_cp1_registers() now, i.e. check for odd fpu register
access when Status.FR = 0.

>          {
>              TCGv_i64 fp0 = tcg_temp_new_i64();
>  
> @@ -9851,7 +9848,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
>          opn = "recip.d";
>          break;
>      case OPC_RSQRT_D:
> -        check_cp1_64bitmode(ctx);

same

Thanks,
Leon