From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWkCs-0006q4-BM for qemu-devel@nongnu.org; Tue, 01 Sep 2015 07:58:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZWkCn-0001Of-8x for qemu-devel@nongnu.org; Tue, 01 Sep 2015 07:58:30 -0400 Received: from mail-lb0-x231.google.com ([2a00:1450:4010:c04::231]:35236) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWkCn-0001OP-0h for qemu-devel@nongnu.org; Tue, 01 Sep 2015 07:58:25 -0400 Received: by lbcbn3 with SMTP id bn3so77117380lbc.2 for ; Tue, 01 Sep 2015 04:58:23 -0700 (PDT) References: <55DB560D.5060108@gmail.com> From: Sergey Fedorov Message-ID: <55E592DD.2030302@gmail.com> Date: Tue, 1 Sep 2015 14:58:21 +0300 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] ARM softmmu breakpoint misbehavior List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers 28.08.2015 22:21, Peter Maydell wrote: > I think what we need to do is have the translate-a64.c > code be smarter, and actually generate the real code > if we're not going to really hit the bp. Except that we > don't really have all the info in the flags to know for > sure about that. So we probably need to do something like > generating a call to a helper which checks whether this > bp should hit and doesn't throw the exception unless it > has to, with the actual code for the insn following. > I need to think about how this ought to work... I think we should only generate a CPU breakpoint TCG exception when it is really going to become a CPU exception (or a GDB exception). It could be done by moving the logic of check_breakpoints() to a helper called from TB. > The watchpoint code has a chance of cpu_resume_from_signal > doing the right thing, because we really did have the > code to do the load/store. However I have a feeling this > won't interact properly with the fact that ARM needs > BP_STOP_BEFORE_ACCESS on its watchpoints (unlike x86, which > is where I was looking at when I wrote the ARM wp handling > code.) So we may well be broken there as well in the > case where check_watchpoints() returns false. As of watchpoints, I'm going to check that a bit later as well.