[Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Petar Jovanovic]

From: Petar Jovanovic <petar.jovanovic@imgtec.com>

Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
v2:
- add check_cp1_registers() for recip.d and rsqrt.d, as suggested by Leon A.

 target-mips/translate.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 93cb4f2..15285bc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9294,7 +9294,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         opn = "movn.s";
         break;
     case OPC_RECIP_S:
-        check_cop1x(ctx);
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
@@ -9306,7 +9305,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         opn = "recip.s";
         break;
     case OPC_RSQRT_S:
-        check_cop1x(ctx);
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
@@ -9839,7 +9837,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         opn = "movn.d";
         break;
     case OPC_RECIP_D:
-        check_cp1_64bitmode(ctx);
+        check_cp1_registers(ctx, fs | fd);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
@@ -9851,7 +9849,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         opn = "recip.d";
         break;
     case OPC_RSQRT_D:
-        check_cp1_64bitmode(ctx);
+        check_cp1_registers(ctx, fs | fd);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
-- 
1.7.9.5

Re: [Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Leon Alrae]

On 26/08/2015 13:12, Petar Jovanovic wrote:
> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
> 
> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> they require any particular mode for its FPU. This patch removes the checks
> that may break a program that uses these instructions.
> 
> Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
> ---
> v2:
> - add check_cp1_registers() for recip.d and rsqrt.d, as suggested by Leon A.
> 
>  target-mips/translate.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)

Applied to mips-next, thanks.

Leon

Re: [Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Aurelien Jarno]

(sorry for the late answer)

On 2015-08-26 14:12, Petar Jovanovic wrote:
> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
> 
> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> they require any particular mode for its FPU. This patch removes the checks
> that may break a program that uses these instructions.

That is correct. That said these instructions do require at least a
MIPS32R2 or a MIPS64R1 CPU. I guess we should add these checks now that
check_cop1x do not guard them anymore.

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Leon Alrae]

On 11/10/15 21:30, Aurelien Jarno wrote:
> (sorry for the late answer)
> 
> On 2015-08-26 14:12, Petar Jovanovic wrote:
>> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
>>
>> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
>> they require any particular mode for its FPU. This patch removes the checks
>> that may break a program that uses these instructions.
> 
> That is correct. That said these instructions do require at least a
> MIPS32R2 or a MIPS64R1 CPU. I guess we should add these checks now that
> check_cop1x do not guard them anymore.

I suspect that this might too restrictive if we take into account also
legacy processors. As far as I know these instructions were already
present in MIPS IV implementations. I think it'll be safer if for the
pre-MIPS32R2 and pre-MIPS64R1 CPUs we keep the check_cop1x. (actually
I'm not certain if check_cop1x is correct, but at least we aren't
relaxing the previous restrictions too much).

Regards,
Leon

Re: [Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Leon Alrae]

Oops my email client dropped Aurelien's email from CC for some reason...
(adding back)

On 19/10/15 17:40, Leon Alrae wrote:
> On 11/10/15 21:30, Aurelien Jarno wrote:
>> (sorry for the late answer)
>>
>> On 2015-08-26 14:12, Petar Jovanovic wrote:
>>> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
>>>
>>> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
>>> they require any particular mode for its FPU. This patch removes the checks
>>> that may break a program that uses these instructions.
>>
>> That is correct. That said these instructions do require at least a
>> MIPS32R2 or a MIPS64R1 CPU. I guess we should add these checks now that
>> check_cop1x do not guard them anymore.
> 
> I suspect that this might too restrictive if we take into account also
> legacy processors. As far as I know these instructions were already
> present in MIPS IV implementations. I think it'll be safer if for the
> pre-MIPS32R2 and pre-MIPS64R1 CPUs we keep the check_cop1x. (actually
> I'm not certain if check_cop1x is correct, but at least we aren't
> relaxing the previous restrictions too much).
> 
> Regards,
> Leon
> 

Re: [Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Maciej W. Rozycki]

On Mon, 19 Oct 2015, Leon Alrae wrote:

> >> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> >> they require any particular mode for its FPU. This patch removes the checks
> >> that may break a program that uses these instructions.
> > 
> > That is correct. That said these instructions do require at least a
> > MIPS32R2 or a MIPS64R1 CPU. I guess we should add these checks now that
> > check_cop1x do not guard them anymore.
> 
> I suspect that this might too restrictive if we take into account also
> legacy processors. As far as I know these instructions were already
> present in MIPS IV implementations. I think it'll be safer if for the
> pre-MIPS32R2 and pre-MIPS64R1 CPUs we keep the check_cop1x. (actually
> I'm not certain if check_cop1x is correct, but at least we aren't
> relaxing the previous restrictions too much).

 These instructions are unrestricted in the MIPS IV ISA[1].  In the 
MIPS64r1 ISA the double-precision variants do require CP0.Status.FR=1[2].  
See also <https://gcc.gnu.org/ml/gcc-patches/2013-11/msg01695.html>.

References:

[1] "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, By 
    Charles Price, September, 1995, pp. B-83, B-86
    <http://techpubs.sgi.com/library/manuals/2000/007-2597-001/pdf/007-2597-001.pdf>

[2] "MIPS Architecture For Programmers, Volume II: The MIPS64 Instruction 
    Set", MIPS Technologies, Inc., Document Number: MD00087, Revision 
    1.00, August 29, 2002, pp. 244, 258

  Maciej