From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZX3vm-0007QW-2I for qemu-devel@nongnu.org; Wed, 02 Sep 2015 05:02:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZX3vh-0000pa-TA for qemu-devel@nongnu.org; Wed, 02 Sep 2015 05:02:10 -0400 Sender: Paolo Bonzini References: <1441138050-5192-1-git-send-email-rth@twiddle.net> From: Paolo Bonzini Message-ID: <55E6BB01.6060800@redhat.com> Date: Wed, 2 Sep 2015 11:01:53 +0200 MIME-Version: 1.0 In-Reply-To: <1441138050-5192-1-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] tcg/aarch64: Fix tcg_out_qemu_{ld, st} for guest_base == 0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: "v2.4.0" , Aurelien Jarno On 01/09/2015 22:07, Richard Henderson wrote: > In ffc6372851d8631a9f9fa56ec613b3244dc635b9, we swapped the guest > base to the address base register from the address index register. > Except that 31 in the base slot is SP not XZR, so we need to be > more intelligent about which reg gets placed in which slot. > > Cc: Paolo Bonzini > Cc: Aurelien Jarno > Cc: Richard Henderson > Cc: qemu-stable@nongnu.org (v2.4.0) > Reported-by: Andreas Färber > Signed-off-by: Richard Henderson > --- > tcg/aarch64/tcg-target.c | 27 ++++++++++++++++++++------- > 1 file changed, 20 insertions(+), 7 deletions(-) > > diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c > index 01ae610..0ed10a9 100644 > --- a/tcg/aarch64/tcg-target.c > +++ b/tcg/aarch64/tcg-target.c > @@ -56,6 +56,11 @@ static const int tcg_target_call_oarg_regs[1] = { > #define TCG_REG_TMP TCG_REG_X30 > > #ifndef CONFIG_SOFTMMU > +/* Note that XZR cannot be encoded in the address base register slot, > + as that actaully encodes SP. So if we need to zero-extend the guest > + address, via the address index register slot, we need to load even > + a zero guest base into a register. */ > +#define USE_GUEST_BASE (guest_base != 0 || TARGET_LONG_BITS == 32) > #define TCG_REG_GUEST_BASE TCG_REG_X28 > #endif > > @@ -1224,9 +1229,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, > add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, > s->code_ptr, label_ptr); > #else /* !CONFIG_SOFTMMU */ > - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, > - guest_base ? TCG_REG_GUEST_BASE : TCG_REG_XZR, > - otype, addr_reg); > + if (USE_GUEST_BASE) { > + tcg_out_qemu_ld_direct(s, memop, ext, data_reg, > + TCG_REG_GUEST_BASE, otype, addr_reg); > + } else { > + tcg_out_qemu_ld_direct(s, memop, ext, data_reg, > + addr_reg, TCG_TYPE_I64, TCG_REG_XZR); > + } > #endif /* CONFIG_SOFTMMU */ > } > > @@ -1245,9 +1254,13 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, > add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64, > data_reg, addr_reg, s->code_ptr, label_ptr); > #else /* !CONFIG_SOFTMMU */ > - tcg_out_qemu_st_direct(s, memop, data_reg, > - guest_base ? TCG_REG_GUEST_BASE : TCG_REG_XZR, > - otype, addr_reg); > + if (USE_GUEST_BASE) { > + tcg_out_qemu_st_direct(s, memop, data_reg, > + TCG_REG_GUEST_BASE, otype, addr_reg); > + } else { > + tcg_out_qemu_st_direct(s, memop, data_reg, > + addr_reg, TCG_TYPE_I64, TCG_REG_XZR); > + } > #endif /* CONFIG_SOFTMMU */ > } > > @@ -1806,7 +1819,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) > CPU_TEMP_BUF_NLONGS * sizeof(long)); > > #if !defined(CONFIG_SOFTMMU) > - if (guest_base) { > + if (USE_GUEST_BASE) { > tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); > tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); > } > Reviewed-by: Paolo Bonzini