From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>,
Gavin Shan <gwshan@linux.vnet.ibm.com>,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [Qemu-devel] [PATCH qemu 1/2] spapr_pci_vfio: Remove redundant spapr-pci-vfio-host-bridge
Date: Wed, 2 Sep 2015 19:44:07 +1000 [thread overview]
Message-ID: <55E6C4E7.9070203@ozlabs.ru> (raw)
In-Reply-To: <1441181763-4400-2-git-send-email-aik@ozlabs.ru>
On 09/02/2015 06:16 PM, Alexey Kardashevskiy wrote:
> sPAPRTCETable is handling 2 TCE tables already:
>
> 1) guest view of the TCE table - emulated devices use only this table;
>
> 2) hardware IOMMU table - VFIO PCI devices use it for actual work but
> it does not replace 1) and it is not visible to the guest.
> The initialization of this table is driven by vfio-pci device,
> DMA map/unmap requests are handled via MemoryListener so there is very
> little to do in spapr-pci-vfio-host-bridge.
>
> This moves VFIO bits to the generic spapr-pci-host-bridge which allows
> putting emulated and VFIO devices on the same PHB. It is still possible
> to create multiple PHBs and avoid sharing PHB resouces for emulated and
> VFIO devices.
>
> If there is no VFIO-PCI device attaches, no special ioctls will be called.
> If there are some VFIO-PCI devices attached, PHB may refuse to attach
> another VFIO-PCI device if a VFIO container on the host kernel side
> does not support container sharing.
>
> This makes spapr-pci-vfio-host-bridge type equal to spapr-pci-host-bridge
> except it has an additional "iommu" property so spapr-pci-vfio-host-bridge
> still should be used for VFIO devices. The next patch will remove IOMMU ID
> property and allow putting VFIO-PCI devices onto spapr-pci-host-bridge.
>
> This adds a number of VFIO-PCI devices currently attached to a PHB as
> PHB needs to know whether to do DMA setup for VFIO or not. Since
> at the moment of the PHB's realize() invocation we cannot tell yet
> how many VFIO-PCI devices are there (they are not attached yet),
> this moves DMA setup to the reset handler.
>
> This moves PCI device lookup from spapr_phb_vfio_eeh_set_option() to
> rtas_ibm_set_eeh_option() as we need to know if the device is "vfio-pci"
> and decide whether to call spapr_phb_vfio_eeh_set_option() or not.
>
> This should cause no behavioural change.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> hw/ppc/Makefile.objs | 5 +-
> hw/ppc/spapr_pci.c | 170 +++++++++++++++++++++++++-------------------
> hw/ppc/spapr_pci_vfio.c | 144 +++++++++++++++----------------------
> include/hw/pci-host/spapr.h | 23 +++---
> 4 files changed, 164 insertions(+), 178 deletions(-)
>
> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
> index c8ab06e..6c06fcf 100644
> --- a/hw/ppc/Makefile.objs
> +++ b/hw/ppc/Makefile.objs
> @@ -3,10 +3,7 @@ obj-y += ppc.o ppc_booke.o
> # IBM pSeries (sPAPR)
> obj-$(CONFIG_PSERIES) += spapr.o spapr_vio.o spapr_events.o
> obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
> -obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o
> -ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
> -obj-y += spapr_pci_vfio.o
> -endif
> +obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_pci_vfio.o spapr_rtc.o spapr_drc.o
> # PowerPC 4xx boards
> obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o
> obj-y += ppc4xx_pci.o
> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
> index bc30631..12f841f 100644
> --- a/hw/ppc/spapr_pci.c
> +++ b/hw/ppc/spapr_pci.c
> @@ -430,7 +430,6 @@ static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
> target_ulong rets)
> {
> sPAPRPHBState *sphb;
> - sPAPRPHBClass *spc;
> PCIDevice *pdev;
> uint32_t addr, option;
> uint64_t buid;
> @@ -445,7 +444,7 @@ static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
> option = rtas_ld(args, 3);
>
> sphb = spapr_pci_find_phb(spapr, buid);
> - if (!sphb) {
> + if (!sphb || (sphb->vfio_num == 0)) {
> goto param_error_exit;
> }
>
> @@ -455,12 +454,7 @@ static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
> goto param_error_exit;
> }
>
> - spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> - if (!spc->eeh_set_option) {
> - goto param_error_exit;
> - }
> -
> - ret = spc->eeh_set_option(sphb, addr, option);
> + ret = spapr_phb_vfio_eeh_set_option(sphb, pdev, option);
> rtas_st(rets, 0, ret);
> return;
>
> @@ -475,7 +469,6 @@ static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
> target_ulong rets)
> {
> sPAPRPHBState *sphb;
> - sPAPRPHBClass *spc;
> PCIDevice *pdev;
> uint32_t addr, option;
> uint64_t buid;
> @@ -486,12 +479,7 @@ static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
>
> buid = rtas_ldq(args, 1);
> sphb = spapr_pci_find_phb(spapr, buid);
> - if (!sphb) {
> - goto param_error_exit;
> - }
> -
> - spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> - if (!spc->eeh_set_option) {
> + if (!sphb || (sphb->vfio_num == 0)) {
> goto param_error_exit;
> }
>
> @@ -531,7 +519,6 @@ static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
> target_ulong rets)
> {
> sPAPRPHBState *sphb;
> - sPAPRPHBClass *spc;
> uint64_t buid;
> int state, ret;
>
> @@ -541,16 +528,11 @@ static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
>
> buid = rtas_ldq(args, 1);
> sphb = spapr_pci_find_phb(spapr, buid);
> - if (!sphb) {
> + if (!sphb || (sphb->vfio_num == 0)) {
> goto param_error_exit;
> }
>
> - spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> - if (!spc->eeh_get_state) {
> - goto param_error_exit;
> - }
> -
> - ret = spc->eeh_get_state(sphb, &state);
> + ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
> rtas_st(rets, 0, ret);
> if (ret != RTAS_OUT_SUCCESS) {
> return;
> @@ -575,7 +557,6 @@ static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
> target_ulong rets)
> {
> sPAPRPHBState *sphb;
> - sPAPRPHBClass *spc;
> uint32_t option;
> uint64_t buid;
> int ret;
> @@ -587,16 +568,11 @@ static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
> buid = rtas_ldq(args, 1);
> option = rtas_ld(args, 3);
> sphb = spapr_pci_find_phb(spapr, buid);
> - if (!sphb) {
> + if (!sphb || (sphb->vfio_num == 0)) {
> goto param_error_exit;
> }
>
> - spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> - if (!spc->eeh_reset) {
> - goto param_error_exit;
> - }
> -
> - ret = spc->eeh_reset(sphb, option);
> + ret = spapr_phb_vfio_eeh_reset(sphb, option);
> rtas_st(rets, 0, ret);
> return;
>
> @@ -611,7 +587,6 @@ static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
> target_ulong rets)
> {
> sPAPRPHBState *sphb;
> - sPAPRPHBClass *spc;
> uint64_t buid;
> int ret;
>
> @@ -621,16 +596,11 @@ static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
>
> buid = rtas_ldq(args, 1);
> sphb = spapr_pci_find_phb(spapr, buid);
> - if (!sphb) {
> + if (!sphb || (sphb->vfio_num == 0)) {
> goto param_error_exit;
> }
>
> - spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> - if (!spc->eeh_configure) {
> - goto param_error_exit;
> - }
> -
> - ret = spc->eeh_configure(sphb);
> + ret = spapr_phb_vfio_eeh_configure(sphb);
> rtas_st(rets, 0, ret);
> return;
>
> @@ -646,7 +616,6 @@ static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
> target_ulong rets)
> {
> sPAPRPHBState *sphb;
> - sPAPRPHBClass *spc;
> int option;
> uint64_t buid;
>
> @@ -656,12 +625,7 @@ static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
>
> buid = rtas_ldq(args, 1);
> sphb = spapr_pci_find_phb(spapr, buid);
> - if (!sphb) {
> - goto param_error_exit;
> - }
> -
> - spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb);
> - if (!spc->eeh_set_option) {
> + if (!sphb || (sphb->vfio_num == 0)) {
> goto param_error_exit;
> }
>
> @@ -810,6 +774,57 @@ static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
> return buf;
> }
>
> +static void spapr_phb_walk_devices(PCIBus *bus, PCIDevice *pdev, void *opaque)
> +{
> + sPAPRPHBState *sphb = opaque;
> + PCIBus *sec_bus;
> +
> + if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
> + ++sphb->vfio_num;
> + }
> +
> + if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
> + PCI_HEADER_TYPE_BRIDGE)) {
> + return;
> + }
> +
> + sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
> + if (!sec_bus) {
> + return;
> + }
> +
> + pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
> + spapr_phb_walk_devices, sphb);
> +}
> +
> +static int spapr_phb_dma_capabilities_update(sPAPRPHBState *sphb)
> +{
> + int ret;
> + PCIBus *bus = PCI_HOST_BRIDGE(sphb)->bus;
> +
> + sphb->dma32_window_start = 0;
> + sphb->dma32_window_size = SPAPR_PCI_DMA32_SIZE;
> +
> + /* Update the number of VFIO-PCI devices on the PHB */
> + sphb->vfio_num = 0;
> + pci_for_each_device(bus, pci_bus_num(bus), spapr_phb_walk_devices, sphb);
> +
> + if (sphb->vfio_num) {
> + if (sphb->iommugroupid == -1) {
> + error_report("Wrong IOMMU group ID %d", sphb->iommugroupid);
> + return -1;
> + }
> +
> + ret = spapr_phb_vfio_dma_capabilities_update(sphb);
> + if (ret) {
> + error_report("Unable to get DMA32 info from VFIO");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> /* Macros to operate with address in OF binding to PCI */
> #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
> #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
> @@ -1217,7 +1232,6 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
> SysBusDevice *s = SYS_BUS_DEVICE(dev);
> sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
> - sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s);
> char *namebuf;
> int i;
> PCIBus *bus;
> @@ -1371,35 +1385,9 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
> }
> }
>
> - if (!info->finish_realize) {
> - error_setg(errp, "finish_realize not defined");
> - return;
> - }
> -
> - info->finish_realize(sphb, errp);
> -
> sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
> }
>
> -static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp)
> -{
> - sPAPRTCETable *tcet;
> - uint32_t nb_table;
> -
> - nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT;
> - tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn,
> - 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false);
> - if (!tcet) {
> - error_setg(errp, "Unable to create TCE table for %s",
> - sphb->dtbusname);
> - return ;
> - }
> -
> - /* Register default 32bit DMA window */
> - memory_region_add_subregion(&sphb->iommu_root, 0,
> - spapr_tce_get_iommu(tcet));
> -}
> -
> static int spapr_phb_children_reset(Object *child, void *opaque)
> {
> DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
> @@ -1413,8 +1401,42 @@ static int spapr_phb_children_reset(Object *child, void *opaque)
>
> static void spapr_phb_reset(DeviceState *qdev)
> {
> + sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
> + sPAPRTCETable *tcet;
> +
> /* Reset the IOMMU state */
> object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
> +
> + if (spapr_phb_dma_capabilities_update(sphb)) {
> + return;
> + }
> +
> + /* Register default 32bit DMA window */
> + tcet = spapr_tce_find_by_liobn(sphb->dma_liobn);
> + if (!tcet) {
> + const unsigned nb = sphb->dma32_window_size >> SPAPR_TCE_PAGE_SHIFT;
> + tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn,
> + sphb->dma32_window_start,
> + SPAPR_TCE_PAGE_SHIFT, nb,
> + sphb->vfio_num > 0);
> + if (!tcet) {
> + error_report("No default TCE table for %s", sphb->dtbusname);
> + return;
> + }
> +
> + memory_region_add_subregion(&sphb->iommu_root, 0,
Of course bug... should be bus_offset instead of 0. I'll wait a bit for
more reviews and respin later.
> + spapr_tce_get_iommu(tcet));
> + }
> +
> + if (sphb->vfio_num) {
> + /*
> + * The PE might be in frozen state. To reenable the EEH
> + * functionality on it will clean the frozen state, which
> + * ensures that the contained PCI devices will work properly
> + * after reboot.
> + */
> + spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev));
> + }
> }
>
> static Property spapr_phb_properties[] = {
> @@ -1535,7 +1557,6 @@ static void spapr_phb_class_init(ObjectClass *klass, void *data)
> {
> PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
> DeviceClass *dc = DEVICE_CLASS(klass);
> - sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass);
> HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
>
> hc->root_bus_path = spapr_phb_root_bus_path;
> @@ -1545,7 +1566,6 @@ static void spapr_phb_class_init(ObjectClass *klass, void *data)
> dc->vmsd = &vmstate_spapr_pci;
> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> dc->cannot_instantiate_with_device_add_yet = false;
> - spc->finish_realize = spapr_phb_finish_realize;
> hp->plug = spapr_phb_hot_plug_child;
> hp->unplug = spapr_phb_hot_unplug_child;
> }
> diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
> index cca45ed..f94d8a4 100644
> --- a/hw/ppc/spapr_pci_vfio.c
> +++ b/hw/ppc/spapr_pci_vfio.c
> @@ -20,84 +20,47 @@
> #include "hw/ppc/spapr.h"
> #include "hw/pci-host/spapr.h"
> #include "hw/pci/msix.h"
> -#include "linux/vfio.h"
> #include "hw/vfio/vfio.h"
>
> +#ifdef CONFIG_LINUX
> +#include "linux/vfio.h"
> +
> static Property spapr_phb_vfio_properties[] = {
> - DEFINE_PROP_INT32("iommu", sPAPRPHBVFIOState, iommugroupid, -1),
> + DEFINE_PROP_INT32("iommu", sPAPRPHBState, iommugroupid, -1),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static void spapr_phb_vfio_finish_realize(sPAPRPHBState *sphb, Error **errp)
> +int spapr_phb_vfio_dma_capabilities_update(sPAPRPHBState *sphb)
> {
> - sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
> struct vfio_iommu_spapr_tce_info info = { .argsz = sizeof(info) };
> int ret;
> - sPAPRTCETable *tcet;
> - uint32_t liobn = svphb->phb.dma_liobn;
>
> - if (svphb->iommugroupid == -1) {
> - error_setg(errp, "Wrong IOMMU group ID %d", svphb->iommugroupid);
> - return;
> - }
> -
> - ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
> - VFIO_CHECK_EXTENSION,
> - (void *) VFIO_SPAPR_TCE_IOMMU);
> - if (ret != 1) {
> - error_setg_errno(errp, -ret,
> - "spapr-vfio: SPAPR extension is not supported");
> - return;
> - }
> -
> - ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
> + ret = vfio_container_ioctl(&sphb->iommu_as, sphb->iommugroupid,
> VFIO_IOMMU_SPAPR_TCE_GET_INFO, &info);
> if (ret) {
> - error_setg_errno(errp, -ret,
> - "spapr-vfio: get info from container failed");
> - return;
> + return ret;
> }
>
> - tcet = spapr_tce_new_table(DEVICE(sphb), liobn, info.dma32_window_start,
> - SPAPR_TCE_PAGE_SHIFT,
> - info.dma32_window_size >> SPAPR_TCE_PAGE_SHIFT,
> - true);
> - if (!tcet) {
> - error_setg(errp, "spapr-vfio: failed to create VFIO TCE table");
> - return;
> - }
> + sphb->dma32_window_start = info.dma32_window_start;
> + sphb->dma32_window_size = info.dma32_window_size;
>
> - /* Register default 32bit DMA window */
> - memory_region_add_subregion(&sphb->iommu_root, tcet->bus_offset,
> - spapr_tce_get_iommu(tcet));
> + return ret;
> }
>
> -static void spapr_phb_vfio_eeh_reenable(sPAPRPHBVFIOState *svphb)
> +void spapr_phb_vfio_eeh_reenable(sPAPRPHBState *sphb)
> {
> struct vfio_eeh_pe_op op = {
> .argsz = sizeof(op),
> .op = VFIO_EEH_PE_ENABLE
> };
>
> - vfio_container_ioctl(&svphb->phb.iommu_as,
> - svphb->iommugroupid, VFIO_EEH_PE_OP, &op);
> + vfio_container_ioctl(&sphb->iommu_as,
> + sphb->iommugroupid, VFIO_EEH_PE_OP, &op);
> }
>
> -static void spapr_phb_vfio_reset(DeviceState *qdev)
> +int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
> + PCIDevice *pdev, int option)
> {
> - /*
> - * The PE might be in frozen state. To reenable the EEH
> - * functionality on it will clean the frozen state, which
> - * ensures that the contained PCI devices will work properly
> - * after reboot.
> - */
> - spapr_phb_vfio_eeh_reenable(SPAPR_PCI_VFIO_HOST_BRIDGE(qdev));
> -}
> -
> -static int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
> - unsigned int addr, int option)
> -{
> - sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
> struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
> int ret;
>
> @@ -105,25 +68,9 @@ static int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
> case RTAS_EEH_DISABLE:
> op.op = VFIO_EEH_PE_DISABLE;
> break;
> - case RTAS_EEH_ENABLE: {
> - PCIHostState *phb;
> - PCIDevice *pdev;
> -
> - /*
> - * The EEH functionality is enabled on basis of PCI device,
> - * instead of PE. We need check the validity of the PCI
> - * device address.
> - */
> - phb = PCI_HOST_BRIDGE(sphb);
> - pdev = pci_find_device(phb->bus,
> - (addr >> 16) & 0xFF, (addr >> 8) & 0xFF);
> - if (!pdev) {
> - return RTAS_OUT_PARAM_ERROR;
> - }
> -
> + case RTAS_EEH_ENABLE:
> op.op = VFIO_EEH_PE_ENABLE;
> break;
> - }
> case RTAS_EEH_THAW_IO:
> op.op = VFIO_EEH_PE_UNFREEZE_IO;
> break;
> @@ -134,7 +81,7 @@ static int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
> return RTAS_OUT_PARAM_ERROR;
> }
>
> - ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
> + ret = vfio_container_ioctl(&sphb->iommu_as, sphb->iommugroupid,
> VFIO_EEH_PE_OP, &op);
> if (ret < 0) {
> return RTAS_OUT_HW_ERROR;
> @@ -143,14 +90,13 @@ static int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
> return RTAS_OUT_SUCCESS;
> }
>
> -static int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state)
> +int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state)
> {
> - sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
> struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
> int ret;
>
> op.op = VFIO_EEH_PE_GET_STATE;
> - ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
> + ret = vfio_container_ioctl(&sphb->iommu_as, sphb->iommugroupid,
> VFIO_EEH_PE_OP, &op);
> if (ret < 0) {
> return RTAS_OUT_PARAM_ERROR;
> @@ -203,9 +149,8 @@ static void spapr_phb_vfio_eeh_pre_reset(sPAPRPHBState *sphb)
> pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL);
> }
>
> -static int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
> +int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
> {
> - sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
> struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
> int ret;
>
> @@ -225,7 +170,7 @@ static int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
> return RTAS_OUT_PARAM_ERROR;
> }
>
> - ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
> + ret = vfio_container_ioctl(&sphb->iommu_as, sphb->iommugroupid,
> VFIO_EEH_PE_OP, &op);
> if (ret < 0) {
> return RTAS_OUT_HW_ERROR;
> @@ -234,14 +179,13 @@ static int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
> return RTAS_OUT_SUCCESS;
> }
>
> -static int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
> +int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
> {
> - sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
> struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
> int ret;
>
> op.op = VFIO_EEH_PE_CONFIGURE;
> - ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
> + ret = vfio_container_ioctl(&sphb->iommu_as, sphb->iommugroupid,
> VFIO_EEH_PE_OP, &op);
> if (ret < 0) {
> return RTAS_OUT_PARAM_ERROR;
> @@ -253,23 +197,14 @@ static int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
> static void spapr_phb_vfio_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> - sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass);
>
> dc->props = spapr_phb_vfio_properties;
> - dc->reset = spapr_phb_vfio_reset;
> - spc->finish_realize = spapr_phb_vfio_finish_realize;
> - spc->eeh_set_option = spapr_phb_vfio_eeh_set_option;
> - spc->eeh_get_state = spapr_phb_vfio_eeh_get_state;
> - spc->eeh_reset = spapr_phb_vfio_eeh_reset;
> - spc->eeh_configure = spapr_phb_vfio_eeh_configure;
> }
>
> static const TypeInfo spapr_phb_vfio_info = {
> .name = TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE,
> .parent = TYPE_SPAPR_PCI_HOST_BRIDGE,
> - .instance_size = sizeof(sPAPRPHBVFIOState),
> .class_init = spapr_phb_vfio_class_init,
> - .class_size = sizeof(sPAPRPHBClass),
> };
>
> static void spapr_pci_vfio_register_types(void)
> @@ -278,3 +213,36 @@ static void spapr_pci_vfio_register_types(void)
> }
>
> type_init(spapr_pci_vfio_register_types)
> +
> +#else /* !CONFIG_LINUX */
> +
> +int spapr_phb_vfio_dma_capabilities_update(sPAPRPHBState *sphb)
> +{
> + return -EINVAL;
> +}
> +
> +int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
> + PCIDevice *pdev, int option)
> +{
> + return RTAS_OUT_HW_ERROR;
> +}
> +
> +int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state)
> +{
> + return RTAS_OUT_HW_ERROR;
> +}
> +
> +int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
> +{
> + return RTAS_OUT_HW_ERROR;
> +}
> +
> +int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
> +{
> + return RTAS_OUT_HW_ERROR;
> +}
> +
> +void spapr_phb_vfio_eeh_reenable(sPAPRPHBState *sphb)
> +{
> +}
> +#endif
> diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
> index 5322b56..7f3c712 100644
> --- a/include/hw/pci-host/spapr.h
> +++ b/include/hw/pci-host/spapr.h
> @@ -47,12 +47,6 @@ typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState;
>
> struct sPAPRPHBClass {
> PCIHostBridgeClass parent_class;
> -
> - void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
> - int (*eeh_set_option)(sPAPRPHBState *sphb, unsigned int addr, int option);
> - int (*eeh_get_state)(sPAPRPHBState *sphb, int *state);
> - int (*eeh_reset)(sPAPRPHBState *sphb, int option);
> - int (*eeh_configure)(sPAPRPHBState *sphb);
> };
>
> typedef struct spapr_pci_msi {
> @@ -91,12 +85,11 @@ struct sPAPRPHBState {
> spapr_pci_msi_mig *msi_devs;
>
> QLIST_ENTRY(sPAPRPHBState) list;
> -};
>
> -struct sPAPRPHBVFIOState {
> - sPAPRPHBState phb;
> -
> - int32_t iommugroupid;
> + int32_t iommugroupid; /* obsolete */
> + uint32_t dma32_window_start;
> + uint32_t dma32_window_size;
> + unsigned vfio_num;
> };
>
> #define SPAPR_PCI_MAX_INDEX 255
> @@ -138,4 +131,12 @@ sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
> PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
> uint32_t config_addr);
>
> +int spapr_phb_vfio_dma_capabilities_update(sPAPRPHBState *sphb);
> +int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
> + PCIDevice *pdev, int option);
> +int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
> +int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
> +int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
> +void spapr_phb_vfio_eeh_reenable(sPAPRPHBState *sphb);
> +
> #endif /* __HW_SPAPR_PCI_H__ */
>
--
Alexey
next prev parent reply other threads:[~2015-09-02 9:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-02 8:16 [Qemu-devel] [PATCH qemu 0/2] spapr_pci: Merge spapr-vfio-phb into spapr-phb Alexey Kardashevskiy
2015-09-02 8:16 ` [Qemu-devel] [PATCH qemu 1/2] spapr_pci_vfio: Remove redundant spapr-pci-vfio-host-bridge Alexey Kardashevskiy
2015-09-02 9:44 ` Alexey Kardashevskiy [this message]
2015-09-03 2:07 ` David Gibson
2015-09-03 3:14 ` Alexey Kardashevskiy
2015-09-03 2:05 ` David Gibson
2015-09-03 3:19 ` Alexey Kardashevskiy
2015-09-03 3:22 ` David Gibson
2015-09-02 8:16 ` [Qemu-devel] [PATCH qemu 2/2] spapr_pci: Remove constraints about VFIO-PCI devices Alexey Kardashevskiy
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