From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39750) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZYDg8-0000Q8-If for qemu-devel@nongnu.org; Sat, 05 Sep 2015 09:38:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZYDg5-0005hf-Cv for qemu-devel@nongnu.org; Sat, 05 Sep 2015 09:38:48 -0400 Received: from rgout06.bt.lon5.cpcloud.co.uk ([65.20.0.183]:58893) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZYDg5-0005hY-4W for qemu-devel@nongnu.org; Sat, 05 Sep 2015 09:38:45 -0400 Message-ID: <55EAF062.4070209@virgin.net> Date: Sat, 05 Sep 2015 14:38:42 +0100 From: Mike Haben MIME-Version: 1.0 References: <1441272453-23964-1-git-send-email-user@mike-desktop> <55EAD1F8.60107@virgin.net> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] ARM targets: added ARM_FEATURE for Thumb-exception bit in system control register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers Hi Peter, You're quite right, on reading some more I see the correspondence with V7. However... while reading up on the Cortex-M3/4/7, I also found "Only Thumb and Thumb-2 instruction sets are supported in Cortex-M architectures, but the legacy 32-bit ARM instruction set isn't supported". Ugh - to avoid storing up a problem for the future, I think I better think it out again! best regards, Mike H. On 05/09/15 14:02, Peter Maydell wrote: > On 5 September 2015 at 12:28, Mike Haben wrote: >> Most ARM cores switch unconditionally to ARM mode when an exception occurs; >> some Cortex variants have a "Thumb-exception enable" bit in the system >> control register that allows an unconditional switch to Thumb mode instead >> when handling exceptions. The presence of this bit seems unrelated to the >> version of instruction set, and some earlier cores use the same bit (30) in >> the control register for a completely different purpose, so seems sensible >> to handle it as yet another ARM feature. > > I think that SCTLR.TE is an ARMv7 feature -- it is documented > in the v7 ARM ARM, and in the v6 ARM ARM the bit is UNP/SBZP. > And the CPUs you've set your new feature bit on in this patch > are exactly the v7 CPUs. > > So I think that we should just change the existing guard > (which requires FEATURE_V4T) to require FEATURE_V7 instead). > You're right that we need to specifically squash env->thumb > to false in the no-feature-present case, though. > > thanks > -- PMM >