From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel
Date: Mon, 7 Sep 2015 22:12:40 -0700 [thread overview]
Message-ID: <55EE6E48.3070806@twiddle.net> (raw)
In-Reply-To: <CAFEAcA9ShVr92O4zSW1_59sqx8wUgbnmhwwjQeYC9NjE+Sd+nQ@mail.gmail.com>
On 09/07/2015 10:17 AM, Peter Maydell wrote:
>> + c64->value = tcg_temp_new_i64();
>> + c64->cond = c32.cond;
>> + if (c32.cond == TCG_COND_EQ || c32.cond == TCG_COND_NE) {
>> + tcg_gen_extu_i32_i64(c64->value, c32.value);
>> + } else {
>> + tcg_gen_ext_i32_i64(c64->value, c32.value);
>> + }
>
> Signed extend would work for EQ and NE as well, wouldn't it?
Yes.
> Why prefer the unsigned extension in those cases? If there's
> a reason, it could do with being commented.
I dunno what I was really thinking there.
r~
next prev parent reply other threads:[~2015-09-08 5:13 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-02 17:57 [Qemu-devel] [PATCH v2 00/11] target-arm improvements for aarch64 Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 01/11] target-arm: Share all common TCG temporaries Richard Henderson
2015-09-07 16:57 ` Peter Maydell
2015-09-08 5:13 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 02/11] target-arm: Introduce DisasCompare Richard Henderson
2015-09-07 17:09 ` Peter Maydell
2015-09-08 5:09 ` Richard Henderson
2015-09-08 8:13 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 03/11] target-arm: Handle always condition codes within arm_test_cc Richard Henderson
2015-09-07 17:11 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel Richard Henderson
2015-09-07 17:17 ` Peter Maydell
2015-09-08 5:12 ` Richard Henderson [this message]
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless Richard Henderson
2015-09-07 17:31 ` Peter Maydell
2015-09-08 5:18 ` Richard Henderson
2015-09-08 8:19 ` Peter Maydell
2015-09-08 15:20 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond Richard Henderson
2015-09-07 17:42 ` Peter Maydell
2015-09-08 15:21 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR Richard Henderson
2015-09-07 17:47 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL Richard Henderson
2015-09-07 18:00 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Richard Henderson
2015-09-07 18:02 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 10/11] target-arm: Recognize ROR Richard Henderson
2015-09-07 18:06 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32 Richard Henderson
2015-09-07 18:11 ` Peter Maydell
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