From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2 01/11] target-arm: Share all common TCG temporaries
Date: Mon, 7 Sep 2015 22:13:12 -0700 [thread overview]
Message-ID: <55EE6E68.5090309@twiddle.net> (raw)
In-Reply-To: <CAFEAcA8jQPuRX-CkZQC0L0z-+SLCUNZvxbqe26WzRhALru-2Fg@mail.gmail.com>
On 09/07/2015 09:57 AM, Peter Maydell wrote:
> On 2 September 2015 at 18:57, Richard Henderson <rth@twiddle.net> wrote:
>> This is a bug fix for aarch64. At present, we have branches using
>> the 32-bit (translate.c) versions of cpu_[NZCV]F, but we set the flags
>> using the 64-bit (translate-a64.c) versions of cpu_[NZCV]F. From
>> the view of the TCG code generator, these are unrelated variables.
>>
>> The bug is hard to see because we currently only read these variables
>> from branches, and upon reaching a branch TCG will first spill live
>> variables and then reload the arguments of the branch. Since the
>> 32-bit versions were never live until reaching the branch, we'd re-read
>> the data that had just been spilled from the 64-bit versions.
>>
>> There is currently no such problem with the cpu_exclusive_* variables,
>> but there's no point in tempting fate.
>>
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> Should this be cc:qemu-stable@nongnu.org ?
Possibly. It's certainly low risk.
r~
next prev parent reply other threads:[~2015-09-08 5:14 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-02 17:57 [Qemu-devel] [PATCH v2 00/11] target-arm improvements for aarch64 Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 01/11] target-arm: Share all common TCG temporaries Richard Henderson
2015-09-07 16:57 ` Peter Maydell
2015-09-08 5:13 ` Richard Henderson [this message]
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 02/11] target-arm: Introduce DisasCompare Richard Henderson
2015-09-07 17:09 ` Peter Maydell
2015-09-08 5:09 ` Richard Henderson
2015-09-08 8:13 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 03/11] target-arm: Handle always condition codes within arm_test_cc Richard Henderson
2015-09-07 17:11 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel Richard Henderson
2015-09-07 17:17 ` Peter Maydell
2015-09-08 5:12 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless Richard Henderson
2015-09-07 17:31 ` Peter Maydell
2015-09-08 5:18 ` Richard Henderson
2015-09-08 8:19 ` Peter Maydell
2015-09-08 15:20 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond Richard Henderson
2015-09-07 17:42 ` Peter Maydell
2015-09-08 15:21 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR Richard Henderson
2015-09-07 17:47 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL Richard Henderson
2015-09-07 18:00 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Richard Henderson
2015-09-07 18:02 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 10/11] target-arm: Recognize ROR Richard Henderson
2015-09-07 18:06 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32 Richard Henderson
2015-09-07 18:11 ` Peter Maydell
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