From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56389) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZBIV-00040a-Or for qemu-devel@nongnu.org; Tue, 08 Sep 2015 01:18:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZBIS-00066F-Ke for qemu-devel@nongnu.org; Tue, 08 Sep 2015 01:18:23 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:35836) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZBIS-000669-GF for qemu-devel@nongnu.org; Tue, 08 Sep 2015 01:18:20 -0400 Received: by pacfv12 with SMTP id fv12so116360569pac.2 for ; Mon, 07 Sep 2015 22:18:19 -0700 (PDT) Sender: Richard Henderson References: <1441216660-8717-1-git-send-email-rth@twiddle.net> <1441216660-8717-6-git-send-email-rth@twiddle.net> From: Richard Henderson Message-ID: <55EE6F99.9040309@twiddle.net> Date: Mon, 7 Sep 2015 22:18:17 -0700 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers On 09/07/2015 10:31 AM, Peter Maydell wrote: >> - if (cond < 0x0e) { /* continue */ >> - gen_set_label(label_continue); >> + /* If COND was false, force the flags to #nzcv. >> + Note that T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0). */ >> + tcg_t1 = tcg_temp_new_i32(); >> + tcg_t2 = tcg_temp_new_i32(); >> + tcg_gen_neg_i32(tcg_t1, tcg_t0); >> + tcg_gen_subi_i32(tcg_t2, tcg_t0, 1); > > t2 is ~t1, right? Do we get better/worse code if we use > tcg_gen_andc_i32(..., tcg_t1) rather than creating t2 and > using gen_and_i32 ? > >> + >> + if (nzcv & 8) { /* N */ >> + tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1); >> + } else { >> + tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2); >> + } >> + if (nzcv & 4) { /* Z */ >> + tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2); >> + } else { >> + tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0); >> + } >> + if (nzcv & 2) { /* C */ >> + tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0); >> + } else { >> + tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2); >> + } >> + if (nzcv & 1) { /* V */ >> + tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1); >> + } else { >> + tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); If the host supports andc, it's probably better to use only the one temp. But otherwise we may save 4 not insns. Is it worth complicating the code for that? r~