From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zb2jp-0006kD-NI for qemu-devel@nongnu.org; Sun, 13 Sep 2015 04:34:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zb2jl-0003sx-Hr for qemu-devel@nongnu.org; Sun, 13 Sep 2015 04:34:17 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:48658) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zb2jl-0003sn-BI for qemu-devel@nongnu.org; Sun, 13 Sep 2015 04:34:13 -0400 References: <25f6c6b5-ea69-4f3c-9c4c-d17a8cebba45@email.android.com> From: Bastian Koppelmann Message-ID: <55F534FC.1030907@mail.uni-paderborn.de> Date: Sun, 13 Sep 2015 10:34:04 +0200 MIME-Version: 1.0 In-Reply-To: <25f6c6b5-ea69-4f3c-9c4c-d17a8cebba45@email.android.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: peter.maydell@linaro.org, Ethan Hunt , qemu-devel On 09/06/2015 10:36 PM, Richard Henderson wrote: > On Sep 5, 2015 14:35, Bastian Koppelmann wrote: >> IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and >> the manual is fairly clear about that. User mode cpu ought not to read >> these registers unconditionally. > When I last discussed this on the openrisc list, back in March, there was no real specification for user mode, and what bits are or should be accessible. > > Looking at > http://opencores.org/or1k/Architecture_Specification > today, that still seems to be the case. > > In the meantime, dropping the privilege check makes linux-user GCC tests work better. > Looking at the article, user mode seems to be optional, so I'm not against it, but it does look weird. How does ork1sim do it? Cheers, Bastian