From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: Richard Henderson <rth@twiddle.net>
Cc: peter.maydell@linaro.org, Ethan Hunt <proljc@gmail.com>,
qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode
Date: Tue, 15 Sep 2015 09:22:48 +0200 [thread overview]
Message-ID: <55F7C748.3030007@mail.uni-paderborn.de> (raw)
In-Reply-To: <55F6FFA5.6080305@twiddle.net>
On 09/14/2015 07:11 PM, Richard Henderson wrote:
> On 09/13/2015 01:34 AM, Bastian Koppelmann wrote:
>> Looking at the article, user mode seems to be optional, so I'm not against it,
>> but it does look weird. How does ork1sim do it?
> It's haphazard. There are checks for supervisor in the l_mtspr and l_mfspr
> insns, but not other uses of the sprs, such as l_rfe.
How about we make the optional user mode a feature bit? This way we are
closer to ork1sim, but don't have the problem that testing is hindered.
Cheers,
Bastian
next prev parent reply other threads:[~2015-09-15 7:22 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-03 0:17 [Qemu-devel] [PATCH 00/17] target-openrisc improvements Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 01/17] target-openrisc: Always enable OPENRISC_DISAS Richard Henderson
2015-09-03 14:15 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 02/17] target-openrisc: Streamline arithmetic and OVE Richard Henderson
2015-09-03 14:16 ` Bastian Koppelmann
2015-09-03 14:44 ` Richard Henderson
2015-09-04 13:12 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 03/17] target-openrisc: Invert the decoding in dec_calc Richard Henderson
2015-09-03 14:48 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 04/17] target-openrisc: Keep SR_F in a separate variable Richard Henderson
2015-09-03 15:09 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 05/17] target-openrisc: Use movcond where appropriate Richard Henderson
2015-09-03 16:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 06/17] target-openrisc: Put SR[OVE] in TB flags Richard Henderson
2015-09-04 13:05 ` Bastian Koppelmann
2015-09-04 14:29 ` Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2015-09-04 13:33 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 08/17] target-openrisc: Set flags on helpers Richard Henderson
2015-09-04 13:58 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit Richard Henderson
2015-09-04 13:59 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2015-09-04 15:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction Richard Henderson
2015-09-04 15:24 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode Richard Henderson
2015-09-05 21:35 ` Bastian Koppelmann
2015-09-06 20:36 ` Richard Henderson
2015-09-13 8:34 ` Bastian Koppelmann
2015-09-14 17:11 ` Richard Henderson
2015-09-15 7:22 ` Bastian Koppelmann [this message]
2015-09-03 0:17 ` [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for " Richard Henderson
2015-09-06 9:30 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2015-09-06 11:38 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd Richard Henderson
2015-09-13 8:21 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception Richard Henderson
2015-09-15 13:02 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa Richard Henderson
2015-09-15 13:04 ` Bastian Koppelmann
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