[Qemu-devel] [PATCH] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions

[Qemu-devel] [PATCH] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions

[gang.chen.5i5j]

From: Chen Gang <gang.chen.5i5j@gmail.com>

Only according to the v1shl, v1shru, and v1shrs implementations.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
---
 target-tilegx/helper.h      |  6 +++++
 target-tilegx/simd_helper.c | 62 +++++++++++++++++++++++++++++++++++++++++++++
 target-tilegx/translate.c   | 20 +++++++++++++++
 3 files changed, 88 insertions(+)

diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 766f5f2..15093973 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -8,3 +8,9 @@ DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
 DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v4shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v4shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v4shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index b931929..6546337 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -32,6 +32,24 @@ uint64_t helper_v1shl(uint64_t a, uint64_t b)
     return (a & m) << b;
 }
 
+uint64_t helper_v2shl(uint64_t a, uint64_t b)
+{
+    uint64_t m;
+
+    b &= 15;
+    m = 0x0001000100010001ULL * (0xffff >> b);
+    return (a & m) << b;
+}
+
+uint64_t helper_v4shl(uint64_t a, uint64_t b)
+{
+    uint64_t m;
+
+    b &= 63;
+    m = 0x0000000100000001ULL * (0xffffffff >> b);
+    return (a & m) << b;
+}
+
 uint64_t helper_v1shru(uint64_t a, uint64_t b)
 {
     uint64_t m;
@@ -41,6 +59,24 @@ uint64_t helper_v1shru(uint64_t a, uint64_t b)
     return (a & m) >> b;
 }
 
+uint64_t helper_v2shru(uint64_t a, uint64_t b)
+{
+    uint64_t m;
+
+    b &= 15;
+    m = 0x0001000100010001ULL * ((0xffff << b) & 0xffff);
+    return (a & m) >> b;
+}
+
+uint64_t helper_v4shru(uint64_t a, uint64_t b)
+{
+    uint64_t m;
+
+    b &= 63;
+    m = 0x0000000100000001ULL * ((0xffffffff << b) & 0xffffffff);
+    return (a & m) >> b;
+}
+
 uint64_t helper_v1shrs(uint64_t a, uint64_t b)
 {
     uint64_t r = 0;
@@ -53,3 +89,29 @@ uint64_t helper_v1shrs(uint64_t a, uint64_t b)
     }
     return r;
 }
+
+uint64_t helper_v2shrs(uint64_t a, uint64_t b)
+{
+    uint64_t r = 0;
+    int i;
+
+    b &= 15;
+    for (i = 0; i < 64; i += 16) {
+        int64_t ae = (int16_t)(a >> i);
+        r |= ((ae >> b) & 0xffff) << i;
+    }
+    return r;
+}
+
+uint64_t helper_v4shrs(uint64_t a, uint64_t b)
+{
+    uint64_t r = 0;
+    int i;
+
+    b &= 63;
+    for (i = 0; i < 64; i += 32) {
+        int64_t ae = (int32_t)(a >> i);
+        r |= ((ae >> b) & 0xffffffff) << i;
+    }
+    return r;
+}
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index e70c3e5..c8247ac 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1144,12 +1144,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
     case OE_RRR(V2SADU, 0, X0):
     case OE_RRR(V2SHLSC, 0, X0):
     case OE_RRR(V2SHLSC, 0, X1):
+        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
     case OE_RRR(V2SHL, 0, X0):
     case OE_RRR(V2SHL, 0, X1):
+        gen_helper_v2shl(tdest, tsrca, tsrcb);
+        mnemonic = "v2shl";
+        break;
     case OE_RRR(V2SHRS, 0, X0):
     case OE_RRR(V2SHRS, 0, X1):
+        gen_helper_v2shrs(tdest, tsrca, tsrcb);
+        mnemonic = "v2shrs";
+        break;
     case OE_RRR(V2SHRU, 0, X0):
     case OE_RRR(V2SHRU, 0, X1):
+        gen_helper_v2shru(tdest, tsrca, tsrcb);
+        mnemonic = "v2shru";
+        break;
     case OE_RRR(V2SUBSC, 0, X0):
     case OE_RRR(V2SUBSC, 0, X1):
     case OE_RRR(V2SUB, 0, X0):
@@ -1174,12 +1184,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
     case OE_RRR(V4PACKSC, 0, X1):
     case OE_RRR(V4SHLSC, 0, X0):
     case OE_RRR(V4SHLSC, 0, X1):
+        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
     case OE_RRR(V4SHL, 0, X0):
     case OE_RRR(V4SHL, 0, X1):
+        gen_helper_v4shl(tdest, tsrca, tsrcb);
+        mnemonic = "v4shl";
+        break;
     case OE_RRR(V4SHRS, 0, X0):
     case OE_RRR(V4SHRS, 0, X1):
+        gen_helper_v4shrs(tdest, tsrca, tsrcb);
+        mnemonic = "v4shrs";
+        break;
     case OE_RRR(V4SHRU, 0, X0):
     case OE_RRR(V4SHRU, 0, X1):
+        gen_helper_v4shru(tdest, tsrca, tsrcb);
+        mnemonic = "v4shru";
+        break;
     case OE_RRR(V4SUBSC, 0, X0):
     case OE_RRR(V4SUBSC, 0, X1):
     case OE_RRR(V4SUB, 0, X0):
-- 
1.9.3

Re: [Qemu-devel] [PATCH] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions

[Richard Henderson]

On 09/18/2015 04:41 PM, gang.chen.5i5j@gmail.com wrote:
> +uint64_t helper_v4shl(uint64_t a, uint64_t b)
> +{
> +    uint64_t m;
> +
> +    b &= 63;

31.  All of the v4 functions have the same error.


r~

Re: [Qemu-devel] [PATCH] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions

[Chen Gang]

On 9/19/15 10:09, Richard Henderson wrote:
> On 09/18/2015 04:41 PM, gang.chen.5i5j@gmail.com wrote:
>> +uint64_t helper_v4shl(uint64_t a, uint64_t b)
>> +{
>> +    uint64_t m;
>> +
>> +    b &= 63;
> 
> 31.  All of the v4 functions have the same error.
> 

OK, thank you very much, I shall send patch v2 for it within the 2 days.

And sorry for replying late, (during this week end, I had to do some
personal things -- met some friends, and drunk).


Thanks.
-- 
Chen Gang (陈刚)

Open, share, and attitude like air, water, and life which God blessed