* [PATCH 01/16] hw/misc/aspeed_i3c: Move to i3c directory
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 02/16] hw/i3c: Add bus support Joe Komlodi
` (15 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Moves the Aspeed I3C model and traces into hw/i3c and create I3C build
files.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
---
hw/Kconfig | 1 +
hw/arm/Kconfig | 1 +
hw/i3c/Kconfig | 2 ++
hw/{misc => i3c}/aspeed_i3c.c | 2 +-
hw/i3c/meson.build | 3 +++
hw/i3c/trace-events | 7 +++++++
hw/i3c/trace.h | 1 +
hw/meson.build | 1 +
hw/misc/meson.build | 1 -
hw/misc/trace-events | 6 ------
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/{misc => i3c}/aspeed_i3c.h | 0
meson.build | 1 +
13 files changed, 19 insertions(+), 9 deletions(-)
create mode 100644 hw/i3c/Kconfig
rename hw/{misc => i3c}/aspeed_i3c.c (99%)
create mode 100644 hw/i3c/meson.build
create mode 100644 hw/i3c/trace-events
create mode 100644 hw/i3c/trace.h
rename include/hw/{misc => i3c}/aspeed_i3c.h (100%)
diff --git a/hw/Kconfig b/hw/Kconfig
index ba62ff6417..b7c8c24bfd 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -12,6 +12,7 @@ source dma/Kconfig
source gpio/Kconfig
source hyperv/Kconfig
source i2c/Kconfig
+source i3c/Kconfig
source ide/Kconfig
source input/Kconfig
source intc/Kconfig
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index b5aed4aff5..a6ca5a9c55 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -454,6 +454,7 @@ config ASPEED_SOC
select DS1338
select FTGMAC100
select I2C
+ select I3C
select DPS310
select PCA9552
select SERIAL
diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig
new file mode 100644
index 0000000000..e07fe445c6
--- /dev/null
+++ b/hw/i3c/Kconfig
@@ -0,0 +1,2 @@
+config I3C
+ bool
diff --git a/hw/misc/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
similarity index 99%
rename from hw/misc/aspeed_i3c.c
rename to hw/i3c/aspeed_i3c.c
index f54f5da522..999978fb7d 100644
--- a/hw/misc/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -10,7 +10,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
-#include "hw/misc/aspeed_i3c.h"
+#include "hw/i3c/aspeed_i3c.h"
#include "hw/registerfields.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build
new file mode 100644
index 0000000000..c0c38b4c12
--- /dev/null
+++ b/hw/i3c/meson.build
@@ -0,0 +1,3 @@
+i3c_ss = ss.source_set()
+i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c'))
+softmmu_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss)
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
new file mode 100644
index 0000000000..3ead84eb45
--- /dev/null
+++ b/hw/i3c/trace-events
@@ -0,0 +1,7 @@
+# See docs/devel/tracing.rst for syntax documentation.
+
+# aspeed_i3c.c
+aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64
+aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
+aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
+aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
diff --git a/hw/i3c/trace.h b/hw/i3c/trace.h
new file mode 100644
index 0000000000..9d4a082e19
--- /dev/null
+++ b/hw/i3c/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_i3c.h"
diff --git a/hw/meson.build b/hw/meson.build
index c7ac7d3d75..b3225de5f9 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -12,6 +12,7 @@ subdir('dma')
subdir('gpio')
subdir('hyperv')
subdir('i2c')
+subdir('i3c')
subdir('ide')
subdir('input')
subdir('intc')
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index a40245ad44..f87c56fb87 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -115,7 +115,6 @@ softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c'))
softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_hace.c',
- 'aspeed_i3c.c',
'aspeed_lpc.c',
'aspeed_scu.c',
'aspeed_sbc.c',
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index c47876a902..cc335fc89d 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -205,12 +205,6 @@ armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU wri
# aspeed_xdma.c
aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64
-# aspeed_i3c.c
-aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64
-aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
-aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
-aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
-
# aspeed_sdmc.c
aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 8adff70072..603cebe5b3 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -22,7 +22,7 @@
#include "hw/timer/aspeed_timer.h"
#include "hw/rtc/aspeed_rtc.h"
#include "hw/i2c/aspeed_i2c.h"
-#include "hw/misc/aspeed_i3c.h"
+#include "hw/i3c/aspeed_i3c.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/misc/aspeed_hace.h"
#include "hw/misc/aspeed_sbc.h"
diff --git a/include/hw/misc/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h
similarity index 100%
rename from include/hw/misc/aspeed_i3c.h
rename to include/hw/i3c/aspeed_i3c.h
diff --git a/meson.build b/meson.build
index 29f8644d6d..91f9b4bbe7 100644
--- a/meson.build
+++ b/meson.build
@@ -2979,6 +2979,7 @@ if have_system
'hw/dma',
'hw/hyperv',
'hw/i2c',
+ 'hw/i3c',
'hw/i386',
'hw/i386/xen',
'hw/i386/kvm',
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 02/16] hw/i3c: Add bus support
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
2023-03-31 1:01 ` [PATCH 01/16] hw/misc/aspeed_i3c: Move to i3c directory Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 03/16] hw/i3c/aspeed_i3c: Add more register fields Joe Komlodi
` (14 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds an I3C bus and a target class.
The bus supports:
- I3C data transmission and reception
- CCCs (including ENTDAA)
- IBIs
- legacy I2C transactions
General usage of the bus is similar to I2C. Users are expected to
initialize a bus via i3c_init_bus, and use the bus returned from the
init function to do transactions on the bus.
In order to handle IBIs, the controller provides callbacks to handle
receiving an IBI from a target, receiving (optional) additional IBI
bytes from a target, and handling when a target is done with its IBI.
Similarly, target creation is done via i3c_target_create_simple and
users use the provided I3CTarget to handle transactions.
The target has functions provided that it can use to invoke an IBI and
send additional bytes.
Along with the expected, send, recv, and event callbacks that is
expected of an I3C target, which are similar to I2C, there is a separate
callback for CCC handling.
This is to help encapsulate CCC handling and keep it separate from
target-specific read/write functionality.
To avoid repition for required CCCs among I3C targets, there is some
class-level CCC handling added. The CCC is then passed to the target in
case it needs to handle it in some way.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
---
hw/i3c/core.c | 629 +++++++++++++++++++++++++++++++++++++++++++
hw/i3c/meson.build | 1 +
hw/i3c/trace-events | 16 ++
include/hw/i3c/i3c.h | 275 +++++++++++++++++++
4 files changed, 921 insertions(+)
create mode 100644 hw/i3c/core.c
create mode 100644 include/hw/i3c/i3c.h
diff --git a/hw/i3c/core.c b/hw/i3c/core.c
new file mode 100644
index 0000000000..758dd7141f
--- /dev/null
+++ b/hw/i3c/core.c
@@ -0,0 +1,629 @@
+/*
+ * QEMU I3C bus interface.
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "trace.h"
+#include "hw/i3c/i3c.h"
+#include "hw/qdev-properties.h"
+
+static Property i3c_props[] = {
+ DEFINE_PROP_UINT8("static-address", struct I3CTarget, static_address, 0),
+ DEFINE_PROP_UINT8("dcr", struct I3CTarget, dcr, 0),
+ DEFINE_PROP_UINT8("bcr", struct I3CTarget, bcr, 0),
+ DEFINE_PROP_UINT64("pid", struct I3CTarget, pid, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static const TypeInfo i3c_bus_info = {
+ .name = TYPE_I3C_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(I3CBus),
+ .class_size = sizeof(I3CBusClass),
+};
+
+I3CBus *i3c_init_bus(DeviceState *parent, const char *name)
+{
+ return i3c_init_bus_type(TYPE_I3C_BUS, parent, name);
+}
+
+I3CBus *i3c_init_bus_type(const char *type, DeviceState *parent,
+ const char *name)
+{
+ I3CBus *bus;
+
+ bus = I3C_BUS(qbus_new(type, parent, name));
+ QLIST_INIT(&bus->current_devs);
+ bus->broadcast = false;
+ bus->in_entdaa = false;
+ bus->in_ccc = false;
+
+ /* I2C init. */
+ g_autofree gchar *i2c_bus_name = g_strdup_printf("%s-legacy-i2c", name);
+ bus->i2c_bus = i2c_init_bus(parent, i2c_bus_name);
+
+ return bus;
+}
+
+bool i3c_bus_busy(I3CBus *bus)
+{
+ return !QLIST_EMPTY(&bus->current_devs);
+}
+
+bool i3c_target_match(I3CBus *bus, I3CTarget *target, uint8_t address)
+{
+ /* Once a target has a dynamic address, it only responds to that. */
+ uint8_t targ_addr = target->address ? target->address :
+ target->static_address;
+
+ if (bus->in_entdaa) {
+ if (address != I3C_BROADCAST) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: I3C Address 0x%.2x sent during "
+ "ENTDAA instead of a broadcast address\n",
+ object_get_canonical_path(OBJECT(bus)), address);
+ return false;
+ }
+
+ /*
+ * Targets should only ACK ENTDAA broadcasts if they have no dynamic
+ * address.
+ */
+ if (target->address == 0) {
+ I3CNode *node = g_new(struct I3CNode, 1);
+ node->target = target;
+ QLIST_INSERT_HEAD(&bus->current_devs, node, next);
+ }
+ return target->address == 0;
+ }
+
+ if ((targ_addr == address) || bus->broadcast) {
+ I3CNode *node = g_new(struct I3CNode, 1);
+ node->target = target;
+ QLIST_INSERT_HEAD(&bus->current_devs, node, next);
+ return true;
+ }
+
+ return false;
+}
+
+bool i3c_scan_bus(I3CBus *bus, uint8_t address)
+{
+ BusChild *child;
+ I3CNode *node, *next;
+
+ /* Clear out any devices from a previous (re-)START. */
+ QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
+ QLIST_REMOVE(node, next);
+ g_free(node);
+ }
+
+ QTAILQ_FOREACH(child, &bus->qbus.children, sibling) {
+ DeviceState *qdev = child->child;
+ I3CTarget *target = I3C_TARGET(qdev);
+
+ if (i3c_target_match(bus, target, address)) {
+ return true;
+ }
+ }
+
+ /* No one on the bus could respond. */
+ return false;
+}
+
+/* Class-level event handling, since we do some CCCs at the class level. */
+static int i3c_target_event(I3CTarget *t, enum I3CEvent event)
+{
+ I3CTargetClass *tc = I3C_TARGET_GET_CLASS(t);
+ trace_i3c_target_event(t->address, event);
+
+ if (event == I3C_STOP) {
+ t->curr_ccc = 0;
+ t->ccc_byte_offset = 0;
+ t->in_ccc = false;
+ }
+ return tc->event(t, event);
+}
+
+/*
+ * Sends a START or repeated START and the address for an I3C transaction.
+ *
+ * This function returns 0 if a device on the bus was able to respond to the
+ * address, and non-zero otherwise.
+ * A non-zero return represents a NACK.
+ */
+static int i3c_do_start_transfer(I3CBus *bus, uint8_t address,
+ enum I3CEvent event)
+{
+ I3CTargetClass *tc;
+ I3CNode *node;
+
+ if (address == I3C_BROADCAST) {
+ bus->broadcast = true;
+ /* If we're not in ENTDAA, a broadcast is the start of a new CCC. */
+ if (!bus->in_entdaa) {
+ bus->in_ccc = false;
+ }
+ } else {
+ bus->broadcast = false;
+ }
+
+ /* No one responded to the address, NACK it. */
+ if (!i3c_scan_bus(bus, address)) {
+ return -1;
+ }
+
+ QLIST_FOREACH(node, &bus->current_devs, next) {
+ I3CTarget *t = node->target;
+
+ tc = I3C_TARGET_GET_CLASS(t);
+ if (tc->event) {
+ int rv = i3c_target_event(t, event);
+ if (rv && !bus->broadcast) {
+ return rv;
+ }
+ }
+ }
+
+ return 0;
+}
+
+int i3c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv)
+{
+ trace_i3c_start_transfer(address, is_recv);
+ return i3c_do_start_transfer(bus, address, is_recv
+ ? I3C_START_RECV
+ : I3C_START_SEND);
+}
+
+int i3c_start_recv(I3CBus *bus, uint8_t address)
+{
+ trace_i3c_start_transfer(address, true);
+ return i3c_do_start_transfer(bus, address, I3C_START_RECV);
+}
+
+int i3c_start_send(I3CBus *bus, uint8_t address)
+{
+ trace_i3c_start_transfer(address, false);
+ return i3c_do_start_transfer(bus, address, I3C_START_SEND);
+}
+
+void i3c_end_transfer(I3CBus *bus)
+{
+ I3CTargetClass *tc;
+ I3CNode *node, *next;
+
+ trace_i3c_end_transfer();
+
+ /*
+ * If we're in ENTDAA, we need to notify all devices when ENTDAA is done.
+ * This is because everyone initially participates due to the broadcast,
+ * but gradually drops out as they get assigned addresses.
+ * Since the current_devs list only stores who's currently participating,
+ * and not everyone who previously participated, we send the STOP to all
+ * children.
+ */
+ if (bus->in_entdaa) {
+ BusChild *child;
+
+ QTAILQ_FOREACH(child, &bus->qbus.children, sibling) {
+ DeviceState *qdev = child->child;
+ I3CTarget *t = I3C_TARGET(qdev);
+ tc = I3C_TARGET_GET_CLASS(t);
+ if (tc->event) {
+ i3c_target_event(t, I3C_STOP);
+ }
+ }
+ } else {
+ QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
+ I3CTarget *t = node->target;
+ tc = I3C_TARGET_GET_CLASS(t);
+ if (tc->event) {
+ i3c_target_event(t, I3C_STOP);
+ }
+ QLIST_REMOVE(node, next);
+ g_free(node);
+ }
+ }
+ bus->broadcast = false;
+ bus->in_entdaa = false;
+ bus->in_ccc = false;
+}
+
+/*
+ * Any CCCs that are universal across all I3C devices should be handled here.
+ * Once they're handled, we pass the CCC up to the I3C target to do anything
+ * else it may want with the bytes.
+ */
+static int i3c_target_handle_ccc_write(I3CTarget *t, const uint8_t *data,
+ uint32_t num_to_send, uint32_t *num_sent)
+{
+ I3CTargetClass *tc = I3C_TARGET_GET_CLASS(t);
+ *num_sent = 0;
+
+ /* Is this the start of a new CCC? */
+ if (!t->in_ccc) {
+ t->curr_ccc = *data;
+ t->in_ccc = true;
+ *num_sent = 1;
+ trace_i3c_target_handle_ccc(t->address, t->curr_ccc);
+ }
+
+ switch (t->curr_ccc) {
+ case I3C_CCC_ENTDAA:
+ /*
+ * This is the last byte of ENTDAA, the controller is assigning us an
+ * address.
+ */
+ if (t->ccc_byte_offset == 8) {
+ t->address = *data;
+ t->in_ccc = false;
+ t->curr_ccc = 0;
+ t->ccc_byte_offset = 0;
+ *num_sent = 1;
+ }
+ break;
+ case I3C_CCCD_SETDASA:
+ t->address = t->static_address;
+ break;
+ case I3C_CCC_SETAASA:
+ t->address = t->static_address;
+ break;
+ case I3C_CCC_RSTDAA:
+ t->address = 0;
+ break;
+ case I3C_CCCD_SETNEWDA:
+ /* If this isn't the CCC byte, it's our new address. */
+ if (*num_sent == 0) {
+ t->address = *data;
+ *num_sent = 1;
+ }
+ break;
+ /* Ignore other CCCs it's better to handle on a device-by-device basis. */
+ default:
+ break;
+ }
+ return tc->handle_ccc_write(t, data, num_to_send, num_sent);
+}
+
+int i3c_send_byte(I3CBus *bus, uint8_t data)
+{
+ /*
+ * Ignored, the caller can determine how many were sent based on if this was
+ * ACKed/NACKed.
+ */
+ uint32_t num_sent;
+ return i3c_send(bus, &data, 1, &num_sent);
+}
+
+int i3c_send(I3CBus *bus, const uint8_t *data, uint32_t num_to_send,
+ uint32_t *num_sent)
+{
+ I3CTargetClass *tc;
+ I3CTarget *t;
+ I3CNode *node;
+ int ret = 0;
+
+ /* If this message is a broadcast and no CCC has been found, grab it. */
+ if (bus->broadcast && !bus->in_ccc) {
+ bus->ccc = *data;
+ bus->in_ccc = true;
+ /*
+ * We need to keep track if we're currently in ENTDAA.
+ * On any other CCC, the CCC is over on a RESTART or STOP, but ENTDAA
+ * is only over on a STOP.
+ */
+ if (bus->ccc == I3C_CCC_ENTDAA) {
+ bus->in_entdaa = true;
+ }
+ }
+
+ QLIST_FOREACH(node, &bus->current_devs, next) {
+ t = node->target;
+ tc = I3C_TARGET_GET_CLASS(t);
+ if (bus->in_ccc) {
+ if (!tc->handle_ccc_write) {
+ ret = -1;
+ continue;
+ }
+ ret = i3c_target_handle_ccc_write(t, data, num_to_send, num_sent);
+ /* Targets should only NACK on a direct CCC. */
+ if (ret && !CCC_IS_DIRECT(bus->ccc)) {
+ ret = 0;
+ }
+ } else {
+ if (tc->send) {
+ ret = ret || tc->send(t, data, num_to_send, num_sent);
+ } else {
+ ret = -1;
+ }
+ }
+ }
+
+ trace_i3c_send(*num_sent, num_to_send, ret == 0);
+
+ return ret ? -1 : 0;
+}
+
+static int i3c_target_handle_ccc_read(I3CTarget *t, uint8_t *data,
+ uint32_t num_to_read, uint32_t *num_read)
+{
+ I3CTargetClass *tc = I3C_TARGET_GET_CLASS(t);
+ uint8_t read_count = 0;
+
+ switch (t->curr_ccc) {
+ case I3C_CCC_ENTDAA:
+ /* Return the 6-byte PID, followed by BCR then DCR. */
+ while (t->ccc_byte_offset < 6) {
+ if (read_count >= num_to_read) {
+ break;
+ }
+ data[read_count] = (t->pid >> (t->ccc_byte_offset * 8)) & 0xff;
+ t->ccc_byte_offset++;
+ read_count++;
+ }
+ if (read_count < num_to_read) {
+ data[read_count] = t->bcr;
+ t->ccc_byte_offset++;
+ read_count++;
+ }
+ if (read_count < num_to_read) {
+ data[read_count] = t->dcr;
+ t->ccc_byte_offset++;
+ read_count++;
+ }
+ *num_read = read_count;
+ break;
+ case I3C_CCCD_GETPID:
+ while (t->ccc_byte_offset < 6) {
+ if (read_count >= num_to_read) {
+ break;
+ }
+ data[read_count] = (t->pid >> (t->ccc_byte_offset * 8)) & 0xff;
+ t->ccc_byte_offset++;
+ read_count++;
+ }
+ *num_read = read_count;
+ break;
+ case I3C_CCCD_GETBCR:
+ *data = t->bcr;
+ *num_read = 1;
+ break;
+ case I3C_CCCD_GETDCR:
+ *data = t->dcr;
+ *num_read = 1;
+ break;
+ default:
+ /* Unhandled on the I3CTarget class level. */
+ break;
+ }
+
+ return tc->handle_ccc_read(t, data, num_to_read, num_read);
+}
+
+int i3c_recv_byte(I3CBus *bus, uint8_t *data)
+{
+ /*
+ * Ignored, the caller can determine how many bytes were read based on if
+ * this is ACKed/NACKed.
+ */
+ uint32_t num_read;
+ return i3c_recv(bus, data, 1, &num_read);
+}
+
+int i3c_recv(I3CBus *bus, uint8_t *data, uint32_t num_to_read,
+ uint32_t *num_read)
+{
+ int ret = 0;
+ I3CTargetClass *tc;
+ I3CTarget *t;
+
+ *data = 0xff;
+ if (!QLIST_EMPTY(&bus->current_devs)) {
+ tc = I3C_TARGET_GET_CLASS(QLIST_FIRST(&bus->current_devs)->target);
+ t = QLIST_FIRST(&bus->current_devs)->target;
+ if (bus->in_ccc) {
+ if (!tc->handle_ccc_read) {
+ return -1;
+ }
+ ret = i3c_target_handle_ccc_read(t, data, num_to_read, num_read);
+ } else {
+ if (tc->recv) {
+ /*
+ * Targets cannot NACK on a direct transfer, so the data
+ * is returned directly.
+ */
+ *num_read = tc->recv(t, data, num_to_read);
+ }
+ }
+ }
+
+ trace_i3c_recv(*num_read, num_to_read, ret == 0);
+
+ return ret;
+}
+
+void i3c_nack(I3CBus *bus)
+{
+ I3CTargetClass *tc;
+ I3CNode *node;
+
+ if (QLIST_EMPTY(&bus->current_devs)) {
+ return;
+ }
+
+ QLIST_FOREACH(node, &bus->current_devs, next) {
+ tc = I3C_TARGET_GET_CLASS(node->target);
+ if (tc->event) {
+ i3c_target_event(node->target, I3C_NACK);
+ }
+ }
+}
+
+int i3c_target_send_ibi(I3CTarget *t, uint8_t addr, bool is_recv)
+{
+ I3CBus *bus = I3C_BUS(t->qdev.parent_bus);
+ I3CBusClass *bc = I3C_BUS_GET_CLASS(bus);
+ trace_i3c_target_send_ibi(addr, is_recv);
+ return bc->ibi_handle(bus, t, addr, is_recv);
+}
+
+int i3c_target_send_ibi_bytes(I3CTarget *t, uint8_t data)
+{
+ I3CBus *bus = I3C_BUS(t->qdev.parent_bus);
+ I3CBusClass *bc = I3C_BUS_GET_CLASS(bus);
+ trace_i3c_target_send_ibi_bytes(data);
+ return bc->ibi_recv(bus, data);
+}
+
+int i3c_target_ibi_finish(I3CTarget *t, uint8_t data)
+{
+ I3CBus *bus = I3C_BUS(t->qdev.parent_bus);
+ I3CBusClass *bc = I3C_BUS_GET_CLASS(bus);
+ trace_i3c_target_ibi_finish();
+ return bc->ibi_finish(bus);
+}
+
+static bool i3c_addr_is_rsvd(uint8_t addr)
+{
+ const bool is_rsvd[255] = {
+ [0x00] = true,
+ [0x01] = true,
+ [0x02] = true,
+ [0x3e] = true,
+ [0x5e] = true,
+ [0x6e] = true,
+ [0x76] = true,
+ [0x7a] = true,
+ [0x7c] = true,
+ [0x7e] = true,
+ [0x7f] = true,
+ };
+
+ return is_rsvd[addr];
+}
+
+I3CTarget *i3c_target_new(const char *name, uint8_t addr, uint8_t dcr,
+ uint8_t bcr, uint64_t pid)
+{
+ DeviceState *dev;
+
+ dev = qdev_new(name);
+ qdev_prop_set_uint8(dev, "static-address", addr);
+ qdev_prop_set_uint8(dev, "dcr", dcr);
+ qdev_prop_set_uint8(dev, "bcr", bcr);
+ qdev_prop_set_uint64(dev, "pid", pid);
+
+ if (i3c_addr_is_rsvd(addr)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: I3C target created with reserved "
+ "address 0x%.2x\n",
+ object_get_canonical_path(OBJECT(dev)), addr);
+ }
+ return I3C_TARGET(dev);
+}
+
+bool i3c_target_realize_and_unref(I3CTarget *dev, I3CBus *bus, Error **errp)
+{
+ return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
+}
+
+I3CTarget *i3c_target_create_simple(I3CBus *bus, const char *name, uint8_t addr,
+ uint8_t dcr, uint8_t bcr, uint64_t pid)
+{
+ I3CTarget *dev = i3c_target_new(name, addr, dcr, bcr, pid);
+ dev->address = 0;
+ i3c_target_realize_and_unref(dev, bus, &error_abort);
+
+ return dev;
+}
+
+/* Legacy I2C functions. */
+void legacy_i2c_nack(I3CBus *bus)
+{
+ trace_legacy_i2c_nack();
+ i2c_nack(bus->i2c_bus);
+}
+
+uint8_t legacy_i2c_recv(I3CBus *bus)
+{
+ uint8_t byte = i2c_recv(bus->i2c_bus);
+ trace_legacy_i2c_recv(byte);
+ return byte;
+}
+
+int legacy_i2c_send(I3CBus *bus, uint8_t data)
+{
+ trace_legacy_i2c_send(data);
+ return i2c_send(bus->i2c_bus, data);
+}
+
+int legacy_i2c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv)
+{
+ trace_legacy_i2c_start_transfer(address, is_recv);
+ return i2c_start_transfer(bus->i2c_bus, address, is_recv);
+}
+
+int legacy_i2c_start_recv(I3CBus *bus, uint8_t address)
+{
+ trace_legacy_i2c_start_transfer(address, true);
+ return i2c_start_transfer(bus->i2c_bus, address, /*is_recv=*/true);
+}
+
+int legacy_i2c_start_send(I3CBus *bus, uint8_t address)
+{
+ trace_legacy_i2c_start_transfer(address, false);
+ return i2c_start_transfer(bus->i2c_bus, address, /*is_recv=*/false);
+}
+
+void legacy_i2c_end_transfer(I3CBus *bus)
+{
+ trace_legacy_i2c_end_transfer();
+ i2c_end_transfer(bus->i2c_bus);
+}
+
+I2CSlave *legacy_i2c_device_create_simple(I3CBus *bus, const char *name,
+ uint8_t addr)
+{
+ I2CSlave *dev = i2c_slave_new(name, addr);
+
+ i2c_slave_realize_and_unref(dev, bus->i2c_bus, &error_abort);
+ return dev;
+}
+
+static void i3c_target_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *k = DEVICE_CLASS(klass);
+ set_bit(DEVICE_CATEGORY_MISC, k->categories);
+ k->bus_type = TYPE_I3C_BUS;
+ device_class_set_props(k, i3c_props);
+}
+
+static const TypeInfo i3c_target_type_info = {
+ .name = TYPE_I3C_TARGET,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(I3CTarget),
+ .abstract = true,
+ .class_size = sizeof(I3CTargetClass),
+ .class_init = i3c_target_class_init,
+};
+
+static void i3c_register_types(void)
+{
+ type_register_static(&i3c_bus_info);
+ type_register_static(&i3c_target_type_info);
+}
+
+type_init(i3c_register_types)
diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build
index c0c38b4c12..3599f1a396 100644
--- a/hw/i3c/meson.build
+++ b/hw/i3c/meson.build
@@ -1,3 +1,4 @@
i3c_ss = ss.source_set()
+i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c'))
i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c'))
softmmu_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss)
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
index 3ead84eb45..cdf7cb07f6 100644
--- a/hw/i3c/trace-events
+++ b/hw/i3c/trace-events
@@ -5,3 +5,19 @@ aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 "
aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
+
+# core.c
+i3c_target_event(uint8_t address, uint8_t event) "I3C target 0x%" PRIx8 " event 0x%" PRIx8
+i3c_target_handle_ccc(uint8_t address, uint8_t ccc) "I3C target 0x%" PRIx8 " handling CCC 0x%" PRIx8
+i3c_target_send_ibi(uint8_t address, bool is_recv) "I3C target IBI address 0x%" PRIx8 " RnW=%d"
+i3c_target_send_ibi_bytes(uint8_t byte) "I3C target IBI byte 0x%" PRIx8
+i3c_target_ibi_finish(void) "I3C target IBI finish"
+i3c_start_transfer(uint8_t address, bool is_recv) "I3C START with address 0x%" PRIx8 " is_recv=%d"
+i3c_end_transfer(void) "I3C transfer done"
+i3c_send(uint32_t num_sent, uint32_t num_to_send, bool ack) "I3C send %" PRId32 "/%" PRId32 " bytes, ack=%d"
+i3c_recv(uint32_t num_read, uint32_t num_to_read, bool ack) "I3C recv %" PRId32 "/%" PRId32 " bytes, ack=%d"
+legacy_i2c_nack(void) "Legacy I2C NACK"
+legacy_i2c_recv(uint8_t byte) "Legacy I2C recv 0x%" PRIx8
+legacy_i2c_send(uint8_t byte) "Legacy I2C send 0x%" PRIx8
+legacy_i2c_start_transfer(uint8_t address, bool is_recv) "Legacy I2C START with address 0x%" PRIx8 " is_recv=%d"
+legacy_i2c_end_transfer(void) "Legacy I2C STOP"
diff --git a/include/hw/i3c/i3c.h b/include/hw/i3c/i3c.h
new file mode 100644
index 0000000000..dab74a0e93
--- /dev/null
+++ b/include/hw/i3c/i3c.h
@@ -0,0 +1,275 @@
+/*
+ * QEMU I3C bus interface.
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef QEMU_INCLUDE_HW_I3C_I3C_H_
+#define QEMU_INCLUDE_HW_I3C_I3C_H_
+
+#include "hw/qdev-core.h"
+#include "qom/object.h"
+#include "hw/i2c/i2c.h"
+
+#define TYPE_I3C_TARGET "i3c-target"
+OBJECT_DECLARE_TYPE(I3CTarget, I3CTargetClass, I3C_TARGET)
+
+typedef enum I3CEvent {
+ I3C_START_RECV,
+ I3C_START_SEND,
+ I3C_STOP,
+ I3C_NACK,
+} I3CEvent;
+
+typedef enum I3CCCC {
+ /* Broadcast CCCs */
+ I3C_CCC_ENEC = 0x00,
+ I3C_CCC_DISEC = 0x01,
+ I3C_CCC_ENTAS0 = 0x02,
+ I3C_CCC_ENTAS1 = 0x03,
+ I3C_CCC_ENTAS2 = 0x04,
+ I3C_CCC_ENTAS3 = 0x05,
+ I3C_CCC_RSTDAA = 0x06,
+ I3C_CCC_ENTDAA = 0x07,
+ I3C_CCC_DEFTGTS = 0x08,
+ I3C_CCC_SETMWL = 0x09,
+ I3C_CCC_SETMRL = 0x0a,
+ I3C_CCC_ENTTM = 0x0b,
+ I3C_CCC_SETBUSCON = 0x0c,
+ I3C_CCC_ENDXFER = 0x12,
+ I3C_CCC_ENTHDR0 = 0x20,
+ I3C_CCC_ENTHDR1 = 0x21,
+ I3C_CCC_ENTHDR2 = 0x22,
+ I3C_CCC_ENTHDR3 = 0x23,
+ I3C_CCC_ENTHDR4 = 0x24,
+ I3C_CCC_ENTHDR5 = 0x25,
+ I3C_CCC_ENTHDR6 = 0x26,
+ I3C_CCC_ENTHDR7 = 0x27,
+ I3C_CCC_SETXTIME = 0x28,
+ I3C_CCC_SETAASA = 0x29,
+ I3C_CCC_RSTACT = 0x2a,
+ I3C_CCC_DEFGRPA = 0x2b,
+ I3C_CCC_RSTGRPA = 0x2c,
+ I3C_CCC_MLANE = 0x2d,
+ /* Direct CCCs */
+ I3C_CCCD_ENEC = 0x80,
+ I3C_CCCD_DISEC = 0x81,
+ I3C_CCCD_ENTAS0 = 0x82,
+ I3C_CCCD_ENTAS1 = 0x83,
+ I3C_CCCD_ENTAS2 = 0x84,
+ I3C_CCCD_ENTAS3 = 0x85,
+ I3C_CCCD_SETDASA = 0x87,
+ I3C_CCCD_SETNEWDA = 0x88,
+ I3C_CCCD_SETMWL = 0x89,
+ I3C_CCCD_SETMRL = 0x8a,
+ I3C_CCCD_GETMWL = 0x8b,
+ I3C_CCCD_GETMRL = 0x8c,
+ I3C_CCCD_GETPID = 0x8d,
+ I3C_CCCD_GETBCR = 0x8e,
+ I3C_CCCD_GETDCR = 0x8f,
+ I3C_CCCD_GETSTATUS = 0x90,
+ I3C_CCCD_GETACCCR = 0x91,
+ I3C_CCCD_ENDXFER = 0x92,
+ I3C_CCCD_SETBRGTGT = 0x93,
+ I3C_CCCD_GETMXDS = 0x94,
+ I3C_CCCD_GETCAPS = 0x95,
+ I3C_CCCD_SETROUTE = 0x96,
+ I3C_CCCD_SETXTIME = 0x98,
+ I3C_CCCD_GETXTIME = 0x99,
+ I3C_CCCD_RSTACT = 0x9a,
+ I3C_CCCD_SETGRPA = 0x9b,
+ I3C_CCCD_RSTGRPA = 0x9c,
+ I3C_CCCD_MLANE = 0x9d,
+} I3CCCC;
+
+#define CCC_IS_DIRECT(_ccc) (_ccc & 0x80)
+
+#define I3C_BROADCAST 0x7e
+#define I3C_HJ_ADDR 0x02
+#define I3C_ENTDAA_SIZE 8
+
+struct I3CTargetClass {
+ DeviceClass parent;
+
+ /*
+ * Controller to target. Returns 0 for success, non-zero for NAK or other
+ * error.
+ */
+ int (*send)(I3CTarget *s, const uint8_t *data, uint32_t num_to_send,
+ uint32_t *num_sent);
+ /*
+ * Target to controller. I3C targets are able to terminate reads early, so
+ * this returns the number of bytes read from the target.
+ */
+ uint32_t (*recv)(I3CTarget *s, uint8_t *data, uint32_t num_to_read);
+ /* Notify the target of a bus state change. */
+ int (*event)(I3CTarget *s, enum I3CEvent event);
+ /*
+ * Handle a read CCC transmitted from a controller.
+ * CCCs are I3C commands that I3C targets support.
+ * The target can NACK the CCC if it does not support it.
+ */
+ int (*handle_ccc_read)(I3CTarget *s, uint8_t *data, uint32_t num_to_read,
+ uint32_t *num_read);
+ /*
+ * Handle a write CCC transmitted from a controller.
+ * CCCs are I3C commands that I3C targets support.
+ * The target can NACK the CCC if it does not support it.
+ */
+ int (*handle_ccc_write)(I3CTarget *s, const uint8_t *data,
+ uint32_t num_to_send, uint32_t *num_sent);
+};
+
+struct I3CTarget {
+ DeviceState qdev;
+
+ uint8_t address;
+ uint8_t static_address;
+ uint8_t dcr;
+ uint8_t bcr;
+ uint64_t pid;
+
+ /* CCC State tracking. */
+ I3CCCC curr_ccc;
+ uint8_t ccc_byte_offset;
+ bool in_ccc;
+};
+
+struct I3CNode {
+ I3CTarget *target;
+ QLIST_ENTRY(I3CNode) next;
+};
+
+typedef struct I3CNode I3CNode;
+
+typedef QLIST_HEAD(I3CNodeList, I3CNode) I3CNodeList;
+
+#define TYPE_I3C_BUS "i3c-bus"
+OBJECT_DECLARE_TYPE(I3CBus, I3CBusClass, I3C_BUS)
+
+struct I3CBus {
+ BusState qbus;
+
+ /* Legacy I2C. */
+ I2CBus *i2c_bus;
+
+ I3CNodeList current_devs;
+ bool broadcast;
+ uint8_t ccc;
+ bool in_ccc;
+ bool in_entdaa;
+ uint8_t saved_address;
+};
+
+struct I3CBusClass {
+ DeviceClass parent;
+
+ /* Handle an incoming IBI request from a target */
+ int (*ibi_handle) (I3CBus *bus, I3CTarget *target, uint8_t addr,
+ bool is_recv);
+ /* Receive data from an IBI request */
+ int (*ibi_recv) (I3CBus *bus, uint8_t data);
+ /* Do anything that needs to be done, since the IBI is finished. */
+ int (*ibi_finish) (I3CBus *bus);
+};
+
+I3CBus *i3c_init_bus(DeviceState *parent, const char *name);
+I3CBus *i3c_init_bus_type(const char *type, DeviceState *parent,
+ const char *name);
+void i3c_set_target_address(I3CTarget *dev, uint8_t address);
+bool i3c_bus_busy(I3CBus *bus);
+
+/*
+ * Start a transfer on an I3C bus.
+ * If is_recv is known at compile-time (i.e. a device will always be sending or
+ * will always be receiving at a certain point), prefer to use i3c_start_recv or
+ * i3c_start_send instead.
+ *
+ * Returns 0 on success, non-zero on an error.
+ */
+int i3c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv);
+
+/*
+ * Start a receive transfer on an I3C bus.
+ *
+ * Returns 0 on success, non-zero on an error
+ */
+int i3c_start_recv(I3CBus *bus, uint8_t address);
+
+/*
+ * Start a send transfer on an I3C bus.
+ *
+ * Returns 0 on success, non-zero on an error
+ */
+int i3c_start_send(I3CBus *bus, uint8_t address);
+
+void i3c_end_transfer(I3CBus *bus);
+void i3c_nack(I3CBus *bus);
+int i3c_send_byte(I3CBus *bus, uint8_t data);
+int i3c_send(I3CBus *bus, const uint8_t *data, uint32_t num_to_send,
+ uint32_t *num_sent);
+/*
+ * I3C receives can only NACK on a CCC. The target should NACK a CCC it does not
+ * support.
+ */
+int i3c_recv_byte(I3CBus *bus, uint8_t *data);
+int i3c_recv(I3CBus *bus, uint8_t *data, uint32_t num_to_read,
+ uint32_t *num_read);
+bool i3c_scan_bus(I3CBus *bus, uint8_t address);
+int i3c_do_entdaa(I3CBus *bus, uint8_t address, uint64_t *pid, uint8_t *bcr,
+ uint8_t *dcr);
+int i3c_start_device_transfer(I3CTarget *dev, int send_length);
+bool i3c_target_match(I3CBus *bus, I3CTarget *target, uint8_t address);
+int i3c_target_send_ibi(I3CTarget *t, uint8_t addr, bool is_recv);
+int i3c_target_send_ibi_bytes(I3CTarget *t, uint8_t data);
+int i3c_target_ibi_finish(I3CTarget *t, uint8_t data);
+
+/*
+ * Legacy I2C functions.
+ *
+ * These are wrapper for I2C functions that take in an I3C bus instead of an I2C
+ * bus. Internally they use the I2C bus (and devices attached to it) that's a
+ * part of the I3C bus
+ */
+void legacy_i2c_nack(I3CBus *bus);
+uint8_t legacy_i2c_recv(I3CBus *bus);
+int legacy_i2c_send(I3CBus *bus, uint8_t data);
+int legacy_i2c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv);
+int legacy_i2c_start_recv(I3CBus *bus, uint8_t address);
+int legacy_i2c_start_send(I3CBus *bus, uint8_t address);
+void legacy_i2c_end_transfer(I3CBus *bus);
+I2CSlave *legacy_i2c_device_create_simple(I3CBus *bus, const char *name,
+ uint8_t addr);
+
+/**
+ * Create an I3C Target.
+ *
+ * The target returned from this function still needs to be realized.
+ */
+I3CTarget *i3c_target_new(const char *name, uint8_t addr, uint8_t dcr,
+ uint8_t bcr, uint64_t pid);
+
+/**
+ * Create and realize an I3C target.
+ *
+ * Create the target, initialize it, put it on the specified I3C bus, and
+ * realize it.
+ */
+I3CTarget *i3c_target_create_simple(I3CBus *bus, const char *name,
+ uint8_t addr, uint8_t dcr, uint8_t bcr,
+ uint64_t pid);
+
+/* Realize and drop the reference count on an I3C target. */
+bool i3c_target_realize_and_unref(I3CTarget *dev, I3CBus *bus, Error **errp);
+
+#endif /* QEMU_INCLUDE_HW_I3C_I3C_H_ */
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 03/16] hw/i3c/aspeed_i3c: Add more register fields
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
2023-03-31 1:01 ` [PATCH 01/16] hw/misc/aspeed_i3c: Move to i3c directory Joe Komlodi
2023-03-31 1:01 ` [PATCH 02/16] hw/i3c: Add bus support Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 04/16] hw/i3c/aspeed_i3c: Add more reset values Joe Komlodi
` (13 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds the rest of the fields laid out in the AST26xx datasheet.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/aspeed_i3c.c | 260 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 248 insertions(+), 12 deletions(-)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 999978fb7d..ae247e03bb 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -2,6 +2,7 @@
* ASPEED I3C Controller
*
* Copyright (C) 2021 ASPEED Technology Inc.
+ * Copyright (C) 2023 Google LLC
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
@@ -20,79 +21,314 @@
/* I3C Controller Registers */
REG32(I3C1_REG0, 0x10)
REG32(I3C1_REG1, 0x14)
- FIELD(I3C1_REG1, I2C_MODE, 0, 1)
- FIELD(I3C1_REG1, SA_EN, 15, 1)
+ FIELD(I3C1_REG1, I2C_MODE, 0, 1)
+ FIELD(I3C1_REG1, SLV_TEST_MODE, 1, 1)
+ FIELD(I3C1_REG1, ACT_MODE, 2, 2)
+ FIELD(I3C1_REG1, PENDING_INT, 4, 4)
+ FIELD(I3C1_REG1, SA, 8, 7)
+ FIELD(I3C1_REG1, SA_EN, 15, 1)
+ FIELD(I3C1_REG1, INST_ID, 16, 4)
REG32(I3C2_REG0, 0x20)
REG32(I3C2_REG1, 0x24)
- FIELD(I3C2_REG1, I2C_MODE, 0, 1)
- FIELD(I3C2_REG1, SA_EN, 15, 1)
+ FIELD(I3C2_REG1, I2C_MODE, 0, 1)
+ FIELD(I3C2_REG1, SLV_TEST_MODE, 1, 1)
+ FIELD(I3C2_REG1, ACT_MODE, 2, 2)
+ FIELD(I3C2_REG1, PENDING_INT, 4, 4)
+ FIELD(I3C2_REG1, SA, 8, 7)
+ FIELD(I3C2_REG1, SA_EN, 15, 1)
+ FIELD(I3C2_REG1, INST_ID, 16, 4)
REG32(I3C3_REG0, 0x30)
REG32(I3C3_REG1, 0x34)
- FIELD(I3C3_REG1, I2C_MODE, 0, 1)
- FIELD(I3C3_REG1, SA_EN, 15, 1)
+ FIELD(I3C3_REG1, I2C_MODE, 0, 1)
+ FIELD(I3C3_REG1, SLV_TEST_MODE, 1, 1)
+ FIELD(I3C3_REG1, ACT_MODE, 2, 2)
+ FIELD(I3C3_REG1, PENDING_INT, 4, 4)
+ FIELD(I3C3_REG1, SA, 8, 7)
+ FIELD(I3C3_REG1, SA_EN, 15, 1)
+ FIELD(I3C3_REG1, INST_ID, 16, 4)
REG32(I3C4_REG0, 0x40)
REG32(I3C4_REG1, 0x44)
- FIELD(I3C4_REG1, I2C_MODE, 0, 1)
- FIELD(I3C4_REG1, SA_EN, 15, 1)
+ FIELD(I3C4_REG1, I2C_MODE, 0, 1)
+ FIELD(I3C4_REG1, SLV_TEST_MODE, 1, 1)
+ FIELD(I3C4_REG1, ACT_MODE, 2, 2)
+ FIELD(I3C4_REG1, PENDING_INT, 4, 4)
+ FIELD(I3C4_REG1, SA, 8, 7)
+ FIELD(I3C4_REG1, SA_EN, 15, 1)
+ FIELD(I3C4_REG1, INST_ID, 16, 4)
REG32(I3C5_REG0, 0x50)
REG32(I3C5_REG1, 0x54)
- FIELD(I3C5_REG1, I2C_MODE, 0, 1)
- FIELD(I3C5_REG1, SA_EN, 15, 1)
+ FIELD(I3C5_REG1, I2C_MODE, 0, 1)
+ FIELD(I3C5_REG1, SLV_TEST_MODE, 1, 1)
+ FIELD(I3C5_REG1, ACT_MODE, 2, 2)
+ FIELD(I3C5_REG1, PENDING_INT, 4, 4)
+ FIELD(I3C5_REG1, SA, 8, 7)
+ FIELD(I3C5_REG1, SA_EN, 15, 1)
+ FIELD(I3C5_REG1, INST_ID, 16, 4)
REG32(I3C6_REG0, 0x60)
REG32(I3C6_REG1, 0x64)
- FIELD(I3C6_REG1, I2C_MODE, 0, 1)
- FIELD(I3C6_REG1, SA_EN, 15, 1)
+ FIELD(I3C6_REG1, I2C_MODE, 0, 1)
+ FIELD(I3C6_REG1, SLV_TEST_MODE, 1, 1)
+ FIELD(I3C6_REG1, ACT_MODE, 2, 2)
+ FIELD(I3C6_REG1, PENDING_INT, 4, 4)
+ FIELD(I3C6_REG1, SA, 8, 7)
+ FIELD(I3C6_REG1, SA_EN, 15, 1)
+ FIELD(I3C6_REG1, INST_ID, 16, 4)
/* I3C Device Registers */
REG32(DEVICE_CTRL, 0x00)
+ FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1)
+ FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1)
+ FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1)
+ FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2)
+ FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1)
+ FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1)
+ FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1)
+ FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1)
+ FIELD(DEVICE_CTRL, I3C_EN, 31, 1)
REG32(DEVICE_ADDR, 0x04)
+ FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7)
+ FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1)
+ FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7)
+ FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 15, 1)
REG32(HW_CAPABILITY, 0x08)
+ FIELD(HW_CAPABILITY, ENTDAA, 0, 1)
+ FIELD(HW_CAPABILITY, HDR_DDR, 3, 1)
+ FIELD(HW_CAPABILITY, HDR_TS, 4, 1)
REG32(COMMAND_QUEUE_PORT, 0x0c)
+ FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3)
+ /* Transfer command structure */
+ FIELD(COMMAND_QUEUE_PORT, TID, 3, 4)
+ FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8)
+ FIELD(COMMAND_QUEUE_PORT, CP, 15, 1)
+ FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5)
+ FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3)
+ FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1)
+ FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1)
+ FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1)
+ FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1)
+ FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1)
+ /* Transfer argument data structure */
+ FIELD(COMMAND_QUEUE_PORT, DB, 8, 8)
+ FIELD(COMMAND_QUEUE_PORT, DL, 16, 16)
+ /* Short data argument data structure */
+ FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3)
+ FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8)
+ FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8)
+ FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8)
+ /* Address assignment command structure */
+ /*
+ * bits 3..21 and 26..31 are the same as the transfer command structure, or
+ * marked as reserved.
+ */
+ FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3)
REG32(RESPONSE_QUEUE_PORT, 0x10)
+ FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16)
+ FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8)
+ FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4)
+ FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4)
REG32(RX_TX_DATA_PORT, 0x14)
REG32(IBI_QUEUE_STATUS, 0x18)
+ FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8)
+ FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8)
+ FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1)
+ FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1)
+ FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1)
REG32(IBI_QUEUE_DATA, 0x18)
REG32(QUEUE_THLD_CTRL, 0x1c)
+ FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8);
+ FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8);
+ FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 8);
+ FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8);
REG32(DATA_BUFFER_THLD_CTRL, 0x20)
+ FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3)
+ FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 10, 3)
+ FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3)
+ FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3)
REG32(IBI_QUEUE_CTRL, 0x24)
+ FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1)
+ FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1)
+ FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1)
REG32(IBI_MR_REQ_REJECT, 0x2c)
REG32(IBI_SIR_REQ_REJECT, 0x30)
REG32(RESET_CTRL, 0x34)
+ FIELD(RESET_CTRL, CORE_RESET, 0, 1)
+ FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1)
+ FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1)
+ FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1)
+ FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1)
+ FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1)
REG32(SLV_EVENT_CTRL, 0x38)
+ FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1)
+ FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1)
+ FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1)
+ FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2)
+ FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1)
+ FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1)
REG32(INTR_STATUS, 0x3c)
+ FIELD(INTR_STATUS, TX_THLD, 0, 1)
+ FIELD(INTR_STATUS, RX_THLD, 1, 1)
+ FIELD(INTR_STATUS, IBI_THLD, 2, 1)
+ FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1)
+ FIELD(INTR_STATUS, RESP_RDY, 4, 1)
+ FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1)
+ FIELD(INTR_STATUS, CCC_UPDATED, 6, 1)
+ FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1)
+ FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1)
+ FIELD(INTR_STATUS, DEFSLV, 10, 1)
+ FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1)
+ FIELD(INTR_STATUS, IBI_UPDATED, 12, 1)
+ FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1)
REG32(INTR_STATUS_EN, 0x40)
+ FIELD(INTR_STATUS_EN, TX_THLD, 0, 1)
+ FIELD(INTR_STATUS_EN, RX_THLD, 1, 1)
+ FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1)
+ FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1)
+ FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1)
+ FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1)
+ FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1)
+ FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1)
+ FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1)
+ FIELD(INTR_STATUS_EN, DEFSLV, 10, 1)
+ FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1)
+ FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1)
+ FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1)
REG32(INTR_SIGNAL_EN, 0x44)
+ FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1)
+ FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1)
+ FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1)
+ FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1)
+ FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1)
+ FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1)
+ FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1)
+ FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1)
+ FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1)
+ FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1)
+ FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1)
+ FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1)
+ FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1)
REG32(INTR_FORCE, 0x48)
+ FIELD(INTR_FORCE, TX_THLD, 0, 1)
+ FIELD(INTR_FORCE, RX_THLD, 1, 1)
+ FIELD(INTR_FORCE, IBI_THLD, 2, 1)
+ FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1)
+ FIELD(INTR_FORCE, RESP_RDY, 4, 1)
+ FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1)
+ FIELD(INTR_FORCE, CCC_UPDATED, 6, 1)
+ FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1)
+ FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1)
+ FIELD(INTR_FORCE, DEFSLV, 10, 1)
+ FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1)
+ FIELD(INTR_FORCE, IBI_UPDATED, 12, 1)
+ FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1)
REG32(QUEUE_STATUS_LEVEL, 0x4c)
+ FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8)
+ FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8)
+ FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8)
+ FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5)
REG32(DATA_BUFFER_STATUS_LEVEL, 0x50)
+ FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8)
+ FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8)
REG32(PRESENT_STATE, 0x54)
+ FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1)
+ FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1)
+ FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1)
+ FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6)
+ FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6)
+ FIELD(PRESENT_STATE, CMD_TID, 24, 4)
REG32(CCC_DEVICE_STATUS, 0x58)
+ FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4)
+ FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 4, 2)
+ FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2)
+ FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1)
+ FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1)
+ FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1)
+ FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1)
+ FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1)
REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c)
FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16)
FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16)
REG32(DEV_CHAR_TABLE_POINTER, 0x60)
+ FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12)
+ FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7)
+ FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3)
REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c)
+ FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16)
REG32(SLV_MIPI_PID_VALUE, 0x70)
REG32(SLV_PID_VALUE, 0x74)
+ FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12)
+ FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4)
+ FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16)
REG32(SLV_CHAR_CTRL, 0x78)
+ FIELD(SLV_CHAR_CTRL, BCR, 0, 8)
+ FIELD(SLV_CHAR_CTRL, DCR, 8, 8)
+ FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8)
REG32(SLV_MAX_LEN, 0x7c)
+ FIELD(SLV_MAX_LEN, MWL, 0, 16)
+ FIELD(SLV_MAX_LEN, MRL, 16, 16)
REG32(MAX_READ_TURNAROUND, 0x80)
REG32(MAX_DATA_SPEED, 0x84)
REG32(SLV_DEBUG_STATUS, 0x88)
REG32(SLV_INTR_REQ, 0x8c)
+ FIELD(SLV_INTR_REQ, SIR, 0, 1)
+ FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2)
+ FIELD(SLV_INTR_REQ, MIR, 3, 1)
+ FIELD(SLV_INTR_REQ, IBI_STS, 8, 2)
+REG32(SLV_TSX_SYMBL_TIMING, 0x90)
+ FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6)
REG32(DEVICE_CTRL_EXTENDED, 0xb0)
+ FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2)
+ FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1)
REG32(SCL_I3C_OD_TIMING, 0xb4)
+ FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8)
+ FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8)
REG32(SCL_I3C_PP_TIMING, 0xb8)
+ FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8)
+ FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8)
REG32(SCL_I2C_FM_TIMING, 0xbc)
REG32(SCL_I2C_FMP_TIMING, 0xc0)
+ FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16)
+ FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8)
REG32(SCL_EXT_LCNT_TIMING, 0xc8)
REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc)
REG32(BUS_FREE_TIMING, 0xd4)
REG32(BUS_IDLE_TIMING, 0xd8)
+ FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20)
REG32(I3C_VER_ID, 0xe0)
REG32(I3C_VER_TYPE, 0xe4)
REG32(EXTENDED_CAPABILITY, 0xe8)
+ FIELD(EXTENDED_CAPABILITY, APP_IF_MODE, 0, 2)
+ FIELD(EXTENDED_CAPABILITY, APP_IF_DATA_WIDTH, 2, 2)
+ FIELD(EXTENDED_CAPABILITY, OPERATION_MODE, 4, 2)
+ FIELD(EXTENDED_CAPABILITY, CLK_PERIOD, 8, 6)
REG32(SLAVE_CONFIG, 0xec)
+ FIELD(SLAVE_CONFIG, DMA_EN, 0, 1)
+ FIELD(SLAVE_CONFIG, HJ_CAP, 0, 1)
+ FIELD(SLAVE_CONFIG, CLK_PERIOD, 2, 14)
+/* Device characteristic table fields */
+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200)
+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8)
+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16)
+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8)
+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c)
+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8)
+/* Dev addr table fields */
+REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_HW_CAPABILITY] = 0x000e00bf,
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 04/16] hw/i3c/aspeed_i3c: Add more reset values
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (2 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 03/16] hw/i3c/aspeed_i3c: Add more register fields Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 05/16] hw/i3c/aspeed_i3c: Add register RO field masks Joe Komlodi
` (12 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds reset values for the new registers added.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/aspeed_i3c.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index ae247e03bb..034a17ff8e 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -333,12 +333,29 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_HW_CAPABILITY] = 0x000e00bf,
[R_QUEUE_THLD_CTRL] = 0x01000101,
+ [R_DATA_BUFFER_THLD_CTRL] = 0x01010100,
+ [R_SLV_EVENT_CTRL] = 0x0000000b,
+ [R_QUEUE_STATUS_LEVEL] = 0x00000002,
+ [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010,
+ [R_PRESENT_STATE] = 0x00000003,
[R_I3C_VER_ID] = 0x3130302a,
[R_I3C_VER_TYPE] = 0x6c633033,
[R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280,
[R_DEV_CHAR_TABLE_POINTER] = 0x00020200,
+ [R_SLV_CHAR_CTRL] = 0x00010000,
[A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
[R_SLV_MAX_LEN] = 0x00ff00ff,
+ [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f,
+ [R_SCL_I3C_OD_TIMING] = 0x000a0010,
+ [R_SCL_I3C_PP_TIMING] = 0x000a000a,
+ [R_SCL_I2C_FM_TIMING] = 0x00100010,
+ [R_SCL_I2C_FMP_TIMING] = 0x00100010,
+ [R_SCL_EXT_LCNT_TIMING] = 0x20202020,
+ [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000,
+ [R_BUS_FREE_TIMING] = 0x00200020,
+ [R_BUS_IDLE_TIMING] = 0x00000020,
+ [R_EXTENDED_CAPABILITY] = 0x00000239,
+ [R_SLAVE_CONFIG] = 0x00000023,
};
static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 05/16] hw/i3c/aspeed_i3c: Add register RO field masks
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (3 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 04/16] hw/i3c/aspeed_i3c: Add more reset values Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 06/16] hw/i3c/aspeed_i3c: Treat more registers as read-as-zero Joe Komlodi
` (11 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds read-only field masks for the I3C device and controller registers.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/aspeed_i3c.c | 56 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 034a17ff8e..6f514bef5e 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -330,6 +330,21 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2)
FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
+static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_DEVICE_NR_REGS] = {
+ [R_I3C1_REG0] = 0xfc000000,
+ [R_I3C1_REG1] = 0xfff00000,
+ [R_I3C2_REG0] = 0xfc000000,
+ [R_I3C2_REG1] = 0xfff00000,
+ [R_I3C3_REG0] = 0xfc000000,
+ [R_I3C3_REG1] = 0xfff00000,
+ [R_I3C4_REG0] = 0xfc000000,
+ [R_I3C4_REG1] = 0xfff00000,
+ [R_I3C5_REG0] = 0xfc000000,
+ [R_I3C5_REG1] = 0xfff00000,
+ [R_I3C6_REG0] = 0xfc000000,
+ [R_I3C6_REG1] = 0xfff00000,
+};
+
static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_HW_CAPABILITY] = 0x000e00bf,
[R_QUEUE_THLD_CTRL] = 0x01000101,
@@ -358,6 +373,45 @@ static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_SLAVE_CONFIG] = 0x00000023,
};
+static const uint32_t ast2600_i3c_device_ro[ASPEED_I3C_DEVICE_NR_REGS] = {
+ [R_DEVICE_CTRL] = 0x04fffe00,
+ [R_DEVICE_ADDR] = 0x7f807f80,
+ [R_HW_CAPABILITY] = 0xffffffff,
+ [R_IBI_QUEUE_STATUS] = 0xffffffff,
+ [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8,
+ [R_IBI_QUEUE_CTRL] = 0xfffffff0,
+ [R_RESET_CTRL] = 0xffffffc0,
+ [R_SLV_EVENT_CTRL] = 0xffffff3f,
+ [R_INTR_STATUS] = 0xffff809f,
+ [R_INTR_STATUS_EN] = 0xffff8080,
+ [R_INTR_SIGNAL_EN] = 0xffff8080,
+ [R_INTR_FORCE] = 0xffff8000,
+ [R_QUEUE_STATUS_LEVEL] = 0xffffffff,
+ [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff,
+ [R_PRESENT_STATE] = 0xffffffff,
+ [R_CCC_DEVICE_STATUS] = 0xffffffff,
+ [R_I3C_VER_ID] = 0xffffffff,
+ [R_I3C_VER_TYPE] = 0xffffffff,
+ [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff,
+ [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff,
+ [R_SLV_PID_VALUE] = 0xffff0fff,
+ [R_SLV_CHAR_CTRL] = 0xffffffff,
+ [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff,
+ [R_SLV_MAX_LEN] = 0xffffffff,
+ [R_MAX_READ_TURNAROUND] = 0xffffffff,
+ [R_MAX_DATA_SPEED] = 0xffffffff,
+ [R_SLV_INTR_REQ] = 0xfffffff0,
+ [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0,
+ [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8,
+ [R_SCL_I3C_OD_TIMING] = 0xff00ff00,
+ [R_SCL_I3C_PP_TIMING] = 0xff00ff00,
+ [R_SCL_I2C_FMP_TIMING] = 0xff000000,
+ [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0,
+ [R_BUS_IDLE_TIMING] = 0xfff00000,
+ [R_EXTENDED_CAPABILITY] = 0xffffffff,
+ [R_SLAVE_CONFIG] = 0xffffffff,
+};
+
static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -387,6 +441,7 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
trace_aspeed_i3c_device_write(s->id, offset, value);
+ value &= ~ast2600_i3c_device_ro[addr];
switch (addr) {
case R_HW_CAPABILITY:
case R_RESPONSE_QUEUE_PORT:
@@ -475,6 +530,7 @@ static void aspeed_i3c_write(void *opaque,
addr >>= 2;
+ data &= ~ast2600_i3c_controller_ro[addr];
/* I3C controller register */
switch (addr) {
case R_I3C1_REG1:
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 06/16] hw/i3c/aspeed_i3c: Treat more registers as read-as-zero
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (4 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 05/16] hw/i3c/aspeed_i3c: Add register RO field masks Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 07/16] hw/i3c/aspeed_i3c: Use 32 bits on MMIO writes Joe Komlodi
` (10 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
RESET_CTRL and INTR_FORCE are write-only.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/aspeed_i3c.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 6f514bef5e..79715f462d 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -420,7 +420,10 @@ static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
uint64_t value;
switch (addr) {
+ /* RAZ */
case R_COMMAND_QUEUE_PORT:
+ case R_RESET_CTRL:
+ case R_INTR_FORCE:
value = 0;
break;
default:
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 07/16] hw/i3c/aspeed_i3c: Use 32 bits on MMIO writes
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (5 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 06/16] hw/i3c/aspeed_i3c: Treat more registers as read-as-zero Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 08/16] hw/i3c/aspeed_i3c: Add IRQ MMIO behavior Joe Komlodi
` (9 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
---
hw/i3c/aspeed_i3c.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 79715f462d..2ed09234ff 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -441,10 +441,11 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
{
AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque);
uint32_t addr = offset >> 2;
+ uint32_t val32 = (uint32_t)value;
trace_aspeed_i3c_device_write(s->id, offset, value);
- value &= ~ast2600_i3c_device_ro[addr];
+ val32 &= ~ast2600_i3c_device_ro[addr];
switch (addr) {
case R_HW_CAPABILITY:
case R_RESPONSE_QUEUE_PORT:
@@ -470,7 +471,7 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
case R_RESET_CTRL:
break;
default:
- s->regs[addr] = value;
+ s->regs[addr] = val32;
break;
}
}
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 08/16] hw/i3c/aspeed_i3c: Add IRQ MMIO behavior
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (6 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 07/16] hw/i3c/aspeed_i3c: Use 32 bits on MMIO writes Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 09/16] hw/i3c/aspeed_i3c: Add data TX and RX Joe Komlodi
` (8 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
---
hw/i3c/aspeed_i3c.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 2ed09234ff..b9aa1367d8 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -17,6 +17,8 @@
#include "qapi/error.h"
#include "migration/vmstate.h"
#include "trace.h"
+#include "hw/i3c/i3c.h"
+#include "hw/irq.h"
/* I3C Controller Registers */
REG32(I3C1_REG0, 0x10)
@@ -412,6 +414,46 @@ static const uint32_t ast2600_i3c_device_ro[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_SLAVE_CONFIG] = 0xffffffff,
};
+static void aspeed_i3c_device_update_irq(AspeedI3CDevice *s)
+{
+ bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]);
+ qemu_set_irq(s->irq, level);
+}
+
+static uint32_t aspeed_i3c_device_intr_status_r(AspeedI3CDevice *s)
+{
+ /* Only return the status whose corresponding EN bits are set. */
+ return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN];
+}
+
+static void aspeed_i3c_device_intr_status_w(AspeedI3CDevice *s, uint32_t val)
+{
+ /* INTR_STATUS[13:5] is w1c, other bits are RO. */
+ val &= 0x3fe0;
+ s->regs[R_INTR_STATUS] &= ~val;
+
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_intr_status_en_w(AspeedI3CDevice *s, uint32_t val)
+{
+ s->regs[R_INTR_STATUS_EN] = val;
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_intr_signal_en_w(AspeedI3CDevice *s, uint32_t val)
+{
+ s->regs[R_INTR_SIGNAL_EN] = val;
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_intr_force_w(AspeedI3CDevice *s, uint32_t val)
+{
+ /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */
+ s->regs[R_INTR_STATUS] = val;
+ aspeed_i3c_device_update_irq(s);
+}
+
static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -426,6 +468,9 @@ static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
case R_INTR_FORCE:
value = 0;
break;
+ case R_INTR_STATUS:
+ value = aspeed_i3c_device_intr_status_r(s);
+ break;
default:
value = s->regs[addr];
break;
@@ -470,6 +515,18 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
break;
case R_RESET_CTRL:
break;
+ case R_INTR_STATUS:
+ aspeed_i3c_device_intr_status_w(s, val32);
+ break;
+ case R_INTR_STATUS_EN:
+ aspeed_i3c_device_intr_status_en_w(s, val32);
+ break;
+ case R_INTR_SIGNAL_EN:
+ aspeed_i3c_device_intr_signal_en_w(s, val32);
+ break;
+ case R_INTR_FORCE:
+ aspeed_i3c_device_intr_force_w(s, val32);
+ break;
default:
s->regs[addr] = val32;
break;
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 09/16] hw/i3c/aspeed_i3c: Add data TX and RX
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (7 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 08/16] hw/i3c/aspeed_i3c: Add IRQ MMIO behavior Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-04-03 8:45 ` Jeremy Kerr
2023-03-31 1:01 ` [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling Joe Komlodi
` (7 subsequent siblings)
16 siblings, 1 reply; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
This adds data and CCC transmission, reception, and the associated
queues required for data transmission and reception to happen.
The I3C controller transmits data by the user writing into a command
queue. When the queue has a command and an argument in it, the
controller starts executing the command.
The controller can execute 1 of 3 ways:
1. A larger data transfer that involves using the TX and RX queues. This
is the most common way the controller does transactions.
2. A small data transfer that involves sending a couple bytes passed
into the command queue argument.
3. An address assignment command. This is how the controller does
ENTDAA. When ENTDAA succeeds in assigning an address to a target, it
updates the controller's char table with the target's PID, BCR, and
DCR.
The controller determines what addresses to send by looking at the index
in the device address table specified by the argument in the command
queue. ENTDAA also uses these addresses to assign to targets on the bus.
When the controller is done executing a command, it puts a response in
the response queue indicating how command execution went.
In order for the user to send and receive data to/from the controller,
the user reads/writes to a bidirectional TX/RX port.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/aspeed_i3c.c | 848 ++++++++++++++++++++++++++++++++++++
hw/i3c/trace-events | 10 +
include/hw/i3c/aspeed_i3c.h | 132 ++++++
3 files changed, 990 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index b9aa1367d8..ffe0b21ca0 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -414,12 +414,183 @@ static const uint32_t ast2600_i3c_device_ro[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_SLAVE_CONFIG] = 0xffffffff,
};
+static inline bool aspeed_i3c_device_has_entdaa(AspeedI3CDevice *s)
+{
+ return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, ENTDAA);
+}
+
+static inline bool aspeed_i3c_device_has_hdr_ts(AspeedI3CDevice *s)
+{
+ return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS);
+}
+
+static inline bool aspeed_i3c_device_has_hdr_ddr(AspeedI3CDevice *s)
+{
+ return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_DDR);
+}
+
+static inline bool aspeed_i3c_device_can_transmit(AspeedI3CDevice *s)
+{
+ /*
+ * We can only transmit if we're enabled and the resume bit is cleared.
+ * The resume bit is set on a transaction error, and software must clear it.
+ */
+ return ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_EN) &&
+ !ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_RESUME);
+}
+
+static inline uint8_t aspeed_i3c_device_fifo_threshold_from_reg(uint8_t regval)
+{
+ return regval = regval ? (2 << regval) : 1;
+}
+
static void aspeed_i3c_device_update_irq(AspeedI3CDevice *s)
{
bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]);
qemu_set_irq(s->irq, level);
}
+static void aspeed_i3c_device_end_transfer(AspeedI3CDevice *s, bool is_i2c)
+{
+ if (is_i2c) {
+ legacy_i2c_end_transfer(s->bus);
+ } else {
+ i3c_end_transfer(s->bus);
+ }
+}
+
+static int aspeed_i3c_device_send_start(AspeedI3CDevice *s, uint8_t addr,
+ bool is_recv, bool is_i2c)
+{
+ int ret;
+
+ if (is_i2c) {
+ ret = legacy_i2c_start_transfer(s->bus, addr, is_recv);
+ } else {
+ ret = i3c_start_transfer(s->bus, addr, is_recv);
+ }
+ if (ret) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed on TX with addr 0x%.2x\n",
+ object_get_canonical_path(OBJECT(s)), addr);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_HALT);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
+ ASPEED_I3C_TRANSFER_STATUS_HALT);
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1);
+ ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1);
+ }
+
+ return ret;
+}
+
+static int aspeed_i3c_device_send(AspeedI3CDevice *s, const uint8_t *data,
+ uint32_t num_to_send, uint32_t *num_sent,
+ bool is_i2c)
+{
+ int ret;
+ uint32_t i;
+
+ *num_sent = 0;
+ if (is_i2c) {
+ /* Legacy I2C must be byte-by-byte. */
+ for (i = 0; i < num_to_send; i++) {
+ ret = legacy_i2c_send(s->bus, data[i]);
+ if (ret) {
+ break;
+ }
+ (*num_sent)++;
+ }
+ } else {
+ ret = i3c_send(s->bus, data, num_to_send, num_sent);
+ }
+ if (ret) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed sending byte 0x%.2x\n",
+ object_get_canonical_path(OBJECT(s)), data[*num_sent]);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_HALT);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
+ ASPEED_I3C_TRANSFER_STATUS_HALT);
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1);
+ ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1);
+ }
+
+ trace_aspeed_i3c_device_send(s->id, *num_sent);
+
+ return ret;
+}
+
+static int aspeed_i3c_device_send_byte(AspeedI3CDevice *s, uint8_t byte,
+ bool is_i2c)
+{
+ /*
+ * Ignored, the caller will know if we sent 0 or 1 bytes depending on if
+ * we were ACKed/NACKed.
+ */
+ uint32_t num_sent;
+ return aspeed_i3c_device_send(s, &byte, 1, &num_sent, is_i2c);
+}
+
+static int aspeed_i3c_device_recv_data(AspeedI3CDevice *s, bool is_i2c,
+ uint8_t *data, uint16_t num_to_read,
+ uint32_t *num_read)
+{
+ int ret;
+
+ if (is_i2c) {
+ for (uint16_t i = 0; i < num_to_read; i++) {
+ data[i] = legacy_i2c_recv(s->bus);
+ }
+ /* I2C devices can neither NACK a read, nor end transfers early. */
+ *num_read = num_to_read;
+ trace_aspeed_i3c_device_recv_data(s->id, *num_read);
+ return 0;
+ }
+ /* I3C devices can NACK if the controller sends an unsupported CCC. */
+ ret = i3c_recv(s->bus, data, num_to_read, num_read);
+ if (ret) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed receiving byte\n",
+ object_get_canonical_path(OBJECT(s)));
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_HALT);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
+ ASPEED_I3C_TRANSFER_STATUS_HALT);
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1);
+ ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1);
+ }
+
+ trace_aspeed_i3c_device_recv_data(s->id, *num_read);
+
+ return ret;
+}
+
+static inline bool aspeed_i3c_device_target_is_i2c(AspeedI3CDevice *s,
+ uint16_t offset)
+{
+ uint16_t dev_index = R_DEVICE_ADDR_TABLE_LOC1 + offset;
+ return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1,
+ LEGACY_I2C_DEVICE);
+}
+
+static uint8_t aspeed_i3c_device_target_addr(AspeedI3CDevice *s,
+ uint16_t offset)
+{
+ if (offset > ASPEED_I3C_NR_DEVICES) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Device addr table offset %d out of "
+ "bounds\n", object_get_canonical_path(OBJECT(s)), offset);
+ /* If we're out of bounds, return an address of 0. */
+ return 0;
+ }
+
+ uint16_t dev_index = R_DEVICE_ADDR_TABLE_LOC1 + offset;
+ /* I2C devices use a static address. */
+ if (aspeed_i3c_device_target_is_i2c(s, offset)) {
+ return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1,
+ DEV_STATIC_ADDR);
+ }
+ return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1,
+ DEV_DYNAMIC_ADDR);
+}
+
static uint32_t aspeed_i3c_device_intr_status_r(AspeedI3CDevice *s)
{
/* Only return the status whose corresponding EN bits are set. */
@@ -454,6 +625,54 @@ static void aspeed_i3c_device_intr_force_w(AspeedI3CDevice *s, uint32_t val)
aspeed_i3c_device_update_irq(s);
}
+static uint32_t aspeed_i3c_device_pop_rx(AspeedI3CDevice *s)
+{
+ if (fifo32_is_empty(&s->rx_queue)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read RX FIFO when empty\n",
+ object_get_canonical_path(OBJECT(s)));
+ return 0;
+ }
+
+ uint32_t val = fifo32_pop(&s->rx_queue);
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR,
+ fifo32_num_used(&s->rx_queue));
+
+ /* Threshold is 2^RX_BUF_THLD. */
+ uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL,
+ RX_BUF_THLD);
+ threshold = aspeed_i3c_device_fifo_threshold_from_reg(threshold);
+ if (fifo32_num_used(&s->rx_queue) < threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0);
+ aspeed_i3c_device_update_irq(s);
+ }
+
+ trace_aspeed_i3c_device_pop_rx(s->id, val);
+ return val;
+}
+
+static uint32_t aspeed_i3c_device_resp_queue_port_r(AspeedI3CDevice *s)
+{
+ if (fifo32_is_empty(&s->resp_queue)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read response FIFO when "
+ "empty\n", object_get_canonical_path(OBJECT(s)));
+ return 0;
+ }
+
+ uint32_t val = fifo32_pop(&s->resp_queue);
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+
+ /* Threshold is the register value + 1. */
+ uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ RESP_BUF_THLD) + 1;
+ if (fifo32_num_used(&s->resp_queue) < threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0);
+ aspeed_i3c_device_update_irq(s);
+ }
+
+ return val;
+}
+
static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -471,6 +690,12 @@ static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
case R_INTR_STATUS:
value = aspeed_i3c_device_intr_status_r(s);
break;
+ case R_RX_TX_DATA_PORT:
+ value = aspeed_i3c_device_pop_rx(s);
+ break;
+ case R_RESPONSE_QUEUE_PORT:
+ value = aspeed_i3c_device_resp_queue_port_r(s);
+ break;
default:
value = s->regs[addr];
break;
@@ -481,6 +706,618 @@ static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
return value;
}
+static void aspeed_i3c_device_resp_queue_push(AspeedI3CDevice *s,
+ uint8_t err, uint8_t tid,
+ uint8_t ccc_type,
+ uint16_t data_len)
+{
+ uint32_t val = 0;
+ val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, ERR_STATUS, err);
+ val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, TID, tid);
+ val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, CCCT, ccc_type);
+ val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, DL, data_len);
+ if (!fifo32_is_full(&s->resp_queue)) {
+ trace_aspeed_i3c_device_resp_queue_push(s->id, val);
+ fifo32_push(&s->resp_queue, val);
+ }
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+ /* Threshold is the register value + 1. */
+ uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ RESP_BUF_THLD) + 1;
+ if (fifo32_num_used(&s->resp_queue) >= threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 1);
+ aspeed_i3c_device_update_irq(s);
+ }
+}
+
+static void aspeed_i3c_device_push_tx(AspeedI3CDevice *s, uint32_t val)
+{
+ if (fifo32_is_full(&s->tx_queue)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to TX FIFO when "
+ "full\n", object_get_canonical_path(OBJECT(s)));
+ return;
+ }
+
+ trace_aspeed_i3c_device_push_tx(s->id, val);
+ fifo32_push(&s->tx_queue, val);
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,
+ fifo32_num_free(&s->tx_queue));
+
+ /* Threshold is 2^TX_BUF_THLD. */
+ uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL,
+ TX_BUF_THLD);
+ empty_threshold =
+ aspeed_i3c_device_fifo_threshold_from_reg(empty_threshold);
+ if (fifo32_num_free(&s->tx_queue) < empty_threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 0);
+ aspeed_i3c_device_update_irq(s);
+ }
+}
+
+static uint32_t aspeed_i3c_device_pop_tx(AspeedI3CDevice *s)
+{
+ if (fifo32_is_empty(&s->tx_queue)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to pop from TX FIFO when "
+ "empty\n", object_get_canonical_path(OBJECT(s)));
+ return 0;
+ }
+
+ uint32_t val = fifo32_pop(&s->tx_queue);
+ trace_aspeed_i3c_device_pop_tx(s->id, val);
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,
+ fifo32_num_free(&s->tx_queue));
+
+ /* Threshold is 2^TX_BUF_THLD. */
+ uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL,
+ TX_BUF_THLD);
+ empty_threshold =
+ aspeed_i3c_device_fifo_threshold_from_reg(empty_threshold);
+ if (fifo32_num_free(&s->tx_queue) >= empty_threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1);
+ aspeed_i3c_device_update_irq(s);
+ }
+ return val;
+}
+
+static void aspeed_i3c_device_push_rx(AspeedI3CDevice *s, uint32_t val)
+{
+ if (fifo32_is_full(&s->rx_queue)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to RX FIFO when "
+ "full\n", object_get_canonical_path(OBJECT(s)));
+ return;
+ }
+ trace_aspeed_i3c_device_push_rx(s->id, val);
+ fifo32_push(&s->rx_queue, val);
+
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR,
+ fifo32_num_used(&s->rx_queue));
+ /* Threshold is 2^RX_BUF_THLD. */
+ uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL,
+ RX_BUF_THLD);
+ threshold = aspeed_i3c_device_fifo_threshold_from_reg(threshold);
+ if (fifo32_num_used(&s->rx_queue) >= threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 1);
+ aspeed_i3c_device_update_irq(s);
+ }
+}
+
+static void aspeed_i3c_device_short_transfer(AspeedI3CDevice *s,
+ AspeedI3CTransferCmd cmd,
+ AspeedI3CShortArg arg)
+{
+ uint8_t err = ASPEED_I3C_RESP_QUEUE_ERR_NONE;
+ uint8_t addr = aspeed_i3c_device_target_addr(s, cmd.dev_index);
+ bool is_i2c = aspeed_i3c_device_target_is_i2c(s, cmd.dev_index);
+ uint8_t data[4]; /* Max we can send on a short transfer is 4 bytes. */
+ uint8_t len = 0;
+ uint32_t bytes_sent; /* Ignored on short transfers. */
+
+ /* Can't do reads on a short transfer. */
+ if (cmd.rnw) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Cannot do a read on a short "
+ "transfer\n", object_get_canonical_path(OBJECT(s)));
+ return;
+ }
+
+ if (aspeed_i3c_device_send_start(s, addr, /*is_recv=*/false, is_i2c)) {
+ err = ASPEED_I3C_RESP_QUEUE_ERR_I2C_NACK;
+ goto transfer_done;
+ }
+
+ /* Are we sending a command? */
+ if (cmd.cp) {
+ data[len] = cmd.cmd;
+ len++;
+ /*
+ * byte0 is the defining byte for a command, and is only sent if a
+ * command is present and if the command has a defining byte present.
+ * (byte_strb & 0x01) is always treated as set by the controller, and is
+ * ignored.
+ */
+ if (cmd.dbp) {
+ data[len] += arg.byte0;
+ len++;
+ }
+ }
+
+ /* Send the bytes passed in the argument. */
+ if (arg.byte_strb & 0x02) {
+ data[len] = arg.byte1;
+ len++;
+ }
+ if (arg.byte_strb & 0x04) {
+ data[len] = arg.byte2;
+ len++;
+ }
+
+ if (aspeed_i3c_device_send(s, data, len, &bytes_sent, is_i2c)) {
+ err = ASPEED_I3C_RESP_QUEUE_ERR_I2C_NACK;
+ } else {
+ /* Only go to an idle state on a successful transfer. */
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_IDLE);
+ }
+
+transfer_done:
+ if (cmd.toc) {
+ aspeed_i3c_device_end_transfer(s, is_i2c);
+ }
+ if (cmd.roc) {
+ /*
+ * ccc_type is always 0 in controller mode, data_len is 0 in short
+ * transfers.
+ */
+ aspeed_i3c_device_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0,
+ /*data_len=*/0);
+ }
+}
+
+/* Returns number of bytes transmitted. */
+static uint16_t aspeed_i3c_device_tx(AspeedI3CDevice *s, uint16_t num,
+ bool is_i2c)
+{
+ uint16_t bytes_sent = 0;
+ union {
+ uint8_t b[sizeof(uint32_t)];
+ uint32_t val;
+ } val32;
+
+ while (bytes_sent < num) {
+ val32.val = aspeed_i3c_device_pop_tx(s);
+ for (uint8_t i = 0; i < sizeof(val32.val); i++) {
+ if (aspeed_i3c_device_send_byte(s, val32.b[i], is_i2c)) {
+ return bytes_sent;
+ }
+ bytes_sent++;
+
+ /* We're not sending the full 32-bits, break early. */
+ if (bytes_sent >= num) {
+ break;
+ }
+ }
+ }
+
+ return bytes_sent;
+}
+
+/* Returns number of bytes received. */
+static uint16_t aspeed_i3c_device_rx(AspeedI3CDevice *s, uint16_t num,
+ bool is_i2c)
+{
+ /*
+ * Allocate a temporary buffer to read data from the target.
+ * Zero it and word-align it as well in case we're reading unaligned data.
+ */
+ g_autofree uint8_t *data = g_new0(uint8_t, num + (num & 0x03));
+ uint32_t *data32 = (uint32_t *)data;
+ /*
+ * 32-bits since the I3C API wants a 32-bit number, even though the
+ * controller can only do 16-bit transfers.
+ */
+ uint32_t num_read = 0;
+
+ /* Can NACK if the target receives an unsupported CCC. */
+ if (aspeed_i3c_device_recv_data(s, is_i2c, data, num, &num_read)) {
+ return 0;
+ }
+
+ for (uint16_t i = 0; i < num_read / 4; i++) {
+ aspeed_i3c_device_push_rx(s, *data32);
+ data32++;
+ }
+ /*
+ * If we're pushing data that isn't 32-bit aligned, push what's left.
+ * It's software's responsibility to know what bits are valid in the partial
+ * data.
+ */
+ if (num_read & 0x03) {
+ aspeed_i3c_device_push_rx(s, *data32);
+ }
+
+ return num_read;
+}
+
+static int aspeed_i3c_device_transfer_ccc(AspeedI3CDevice *s,
+ AspeedI3CTransferCmd cmd,
+ AspeedI3CTransferArg arg)
+{
+ /* CCC start is always a write. CCCs cannot be done on I2C devices. */
+ if (aspeed_i3c_device_send_start(s, I3C_BROADCAST, /*is_recv=*/false,
+ /*is_i2c=*/false)) {
+ return ASPEED_I3C_RESP_QUEUE_ERR_BROADCAST_NACK;
+ }
+ trace_aspeed_i3c_device_transfer_ccc(s->id, cmd.cmd);
+ if (aspeed_i3c_device_send_byte(s, cmd.cmd, /*is_i2c=*/false)) {
+ return ASPEED_I3C_RESP_QUEUE_ERR_I2C_NACK;
+ }
+
+ /* On a direct CCC, we do a restart and then send the target's address. */
+ if (CCC_IS_DIRECT(cmd.cmd)) {
+ bool is_recv = cmd.rnw;
+ uint8_t addr = aspeed_i3c_device_target_addr(s, cmd.dev_index);
+ if (aspeed_i3c_device_send_start(s, addr, is_recv, /*is_i2c=*/false)) {
+ return ASPEED_I3C_RESP_QUEUE_ERR_BROADCAST_NACK;
+ }
+ }
+
+ return ASPEED_I3C_RESP_QUEUE_ERR_NONE;
+}
+
+static void aspeed_i3c_device_transfer(AspeedI3CDevice *s,
+ AspeedI3CTransferCmd cmd,
+ AspeedI3CTransferArg arg)
+{
+ bool is_recv = cmd.rnw;
+ uint8_t err = ASPEED_I3C_RESP_QUEUE_ERR_NONE;
+ uint8_t addr = aspeed_i3c_device_target_addr(s, cmd.dev_index);
+ bool is_i2c = aspeed_i3c_device_target_is_i2c(s, cmd.dev_index);
+ uint16_t bytes_transferred = 0;
+
+ if (cmd.cp) {
+ /* We're sending a CCC. */
+ err = aspeed_i3c_device_transfer_ccc(s, cmd, arg);
+ if (err != ASPEED_I3C_RESP_QUEUE_ERR_NONE) {
+ goto transfer_done;
+ }
+ } else {
+ if (ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_BROADCAST_ADDR_INC) &&
+ is_i2c == false) {
+ if (aspeed_i3c_device_send_start(s, I3C_BROADCAST,
+ /*is_recv=*/false, is_i2c)) {
+ err = ASPEED_I3C_RESP_QUEUE_ERR_I2C_NACK;
+ goto transfer_done;
+ }
+ }
+ /* Otherwise we're doing a private transfer. */
+ if (aspeed_i3c_device_send_start(s, addr, is_recv, is_i2c)) {
+ err = ASPEED_I3C_RESP_QUEUE_ERR_I2C_NACK;
+ goto transfer_done;
+ }
+ }
+
+ if (is_recv) {
+ bytes_transferred = aspeed_i3c_device_rx(s, arg.data_len, is_i2c);
+ } else {
+ bytes_transferred = aspeed_i3c_device_tx(s, arg.data_len, is_i2c);
+ }
+
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_IDLE);
+
+transfer_done:
+ if (cmd.toc) {
+ aspeed_i3c_device_end_transfer(s, is_i2c);
+ }
+ if (cmd.roc) {
+ /*
+ * data_len is the number of bytes that still need to be TX'd, or the
+ * number of bytes RX'd.
+ */
+ uint16_t data_len = is_recv ? bytes_transferred : arg.data_len -
+ bytes_transferred;
+ /* CCCT is always 0 in controller mode. */
+ aspeed_i3c_device_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0,
+ data_len);
+ }
+
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_transfer_cmd(AspeedI3CDevice *s,
+ AspeedI3CTransferCmd cmd,
+ AspeedI3CCmdQueueData arg)
+{
+ uint8_t arg_attr = FIELD_EX32(arg.word, COMMAND_QUEUE_PORT, CMD_ATTR);
+
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CMD_TID, cmd.tid);
+
+ /* User is trying to do HDR transfers, see if we can do them. */
+ if (cmd.speed == 0x06 && !aspeed_i3c_device_has_hdr_ddr(s)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR DDR is not supported\n",
+ object_get_canonical_path(OBJECT(s)));
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_HALT);
+ return;
+ }
+ if (cmd.speed == 0x05 && !aspeed_i3c_device_has_hdr_ts(s)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR TS is not supported\n",
+ object_get_canonical_path(OBJECT(s)));
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_HALT);
+ return;
+ }
+
+ if (arg_attr == ASPEED_I3C_CMD_ATTR_TRANSFER_ARG) {
+ aspeed_i3c_device_transfer(s, cmd, arg.transfer_arg);
+ } else if (arg_attr == ASPEED_I3C_CMD_ATTR_SHORT_DATA_ARG) {
+ aspeed_i3c_device_short_transfer(s, cmd, arg.short_arg);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown command queue cmd_attr 0x%x"
+ "\n", object_get_canonical_path(OBJECT(s)), arg_attr);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_HALT);
+ }
+}
+
+static void aspeed_i3c_device_update_char_table(AspeedI3CDevice *s,
+ uint8_t offset, uint64_t pid,
+ uint8_t bcr, uint8_t dcr,
+ uint8_t addr)
+{
+ if (offset > ASPEED_I3C_NR_DEVICES) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Device char table offset %d out of "
+ "bounds\n", object_get_canonical_path(OBJECT(s)), offset);
+ /* If we're out of bounds, do nothing. */
+ return;
+ }
+
+ /* Each char table index is 128 bits apart. */
+ uint16_t dev_index = R_DEVICE_CHARACTERISTIC_TABLE_LOC1 + offset *
+ sizeof(uint32_t);
+ s->regs[dev_index] = pid & 0xffffffff;
+ pid >>= 32;
+ s->regs[dev_index + 1] = FIELD_DP32(s->regs[dev_index + 1],
+ DEVICE_CHARACTERISTIC_TABLE_LOC2,
+ MSB_PID, pid);
+ s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2],
+ DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR,
+ dcr);
+ s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2],
+ DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR,
+ bcr);
+ s->regs[dev_index + 3] = FIELD_DP32(s->regs[dev_index + 3],
+ DEVICE_CHARACTERISTIC_TABLE_LOC4,
+ DEV_DYNAMIC_ADDR, addr);
+
+ /* Increment PRESENT_DEV_CHAR_TABLE_INDEX. */
+ uint8_t idx = ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER,
+ PRESENT_DEV_CHAR_TABLE_INDEX);
+ /* Increment and rollover. */
+ idx++;
+ if (idx >= ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER,
+ DEV_CHAR_TABLE_DEPTH) / 4) {
+ idx = 0;
+ }
+ ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER,
+ PRESENT_DEV_CHAR_TABLE_INDEX, idx);
+}
+
+static void aspeed_i3c_device_addr_assign_cmd(AspeedI3CDevice *s,
+ AspeedI3CAddrAssignCmd cmd)
+{
+ uint8_t i = 0;
+ uint8_t err = ASPEED_I3C_RESP_QUEUE_ERR_NONE;
+
+ if (!aspeed_i3c_device_has_entdaa(s)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: ENTDAA is not supported\n",
+ object_get_canonical_path(OBJECT(s)));
+ return;
+ }
+
+ /* Tell everyone to ENTDAA. If these error, no one is on the bus. */
+ if (aspeed_i3c_device_send_start(s, I3C_BROADCAST, /*is_recv=*/false,
+ /*is_i2c=*/false)) {
+ err = ASPEED_I3C_RESP_QUEUE_ERR_BROADCAST_NACK;
+ goto transfer_done;
+ }
+ if (aspeed_i3c_device_send_byte(s, cmd.cmd, /*is_i2c=*/false)) {
+ err = ASPEED_I3C_RESP_QUEUE_ERR_BROADCAST_NACK;
+ goto transfer_done;
+ }
+
+ /* Go through each device in the table and assign it an address. */
+ for (i = 0; i < cmd.dev_count; i++) {
+ uint8_t addr = aspeed_i3c_device_target_addr(s, cmd.dev_index + i);
+ union {
+ uint64_t pid:48;
+ uint8_t bcr;
+ uint8_t dcr;
+ uint32_t w[2];
+ uint8_t b[8];
+ } target_info;
+
+ /* If this fails, there was no one left to ENTDAA. */
+ if (aspeed_i3c_device_send_start(s, I3C_BROADCAST, /*is_recv=*/false,
+ /*is_i2c=*/false)) {
+ err = ASPEED_I3C_RESP_QUEUE_ERR_BROADCAST_NACK;
+ break;
+ }
+
+ /*
+ * In ENTDAA, we read 8 bytes from the target, which will be the
+ * target's PID, BCR, and DCR. After that, we send it the dynamic
+ * address.
+ * Don't bother checking the number of bytes received, it must send 8
+ * bytes during ENTDAA.
+ */
+ uint32_t num_read;
+ if (aspeed_i3c_device_recv_data(s, /*is_i2c=*/false, target_info.b,
+ I3C_ENTDAA_SIZE, &num_read)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed ENTDAA CCC\n",
+ object_get_canonical_path(OBJECT(s)));
+ err = ASPEED_I3C_RESP_QUEUE_ERR_DAA_NACK;
+ goto transfer_done;
+ }
+ if (aspeed_i3c_device_send_byte(s, addr, /*is_i2c=*/false)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed addr 0x%.2x "
+ "during ENTDAA\n",
+ object_get_canonical_path(OBJECT(s)), addr);
+ err = ASPEED_I3C_RESP_QUEUE_ERR_DAA_NACK;
+ break;
+ }
+ aspeed_i3c_device_update_char_table(s, cmd.dev_index + i,
+ target_info.pid, target_info.bcr,
+ target_info.dcr, addr);
+
+ /* Push the PID, BCR, and DCR to the RX queue. */
+ aspeed_i3c_device_push_rx(s, target_info.w[0]);
+ aspeed_i3c_device_push_rx(s, target_info.w[1]);
+ }
+
+transfer_done:
+ /* Do we send a STOP? */
+ if (cmd.toc) {
+ aspeed_i3c_device_end_transfer(s, /*is_i2c=*/false);
+ }
+ /*
+ * For addr assign commands, the length field is the number of devices
+ * left to assign. CCCT is always 0 in controller mode.
+ */
+ if (cmd.roc) {
+ aspeed_i3c_device_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0,
+ cmd.dev_count - i);
+ }
+}
+
+static uint32_t aspeed_i3c_device_cmd_queue_pop(AspeedI3CDevice *s)
+{
+ if (fifo32_is_empty(&s->cmd_queue)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to dequeue command queue "
+ "when it was empty\n",
+ object_get_canonical_path(OBJECT(s)));
+ return 0;
+ }
+ uint32_t val = fifo32_pop(&s->cmd_queue);
+
+ uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ CMD_BUF_EMPTY_THLD);
+ uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs,
+ QUEUE_STATUS_LEVEL,
+ CMD_QUEUE_EMPTY_LOC);
+ cmd_queue_empty_loc++;
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,
+ cmd_queue_empty_loc);
+ if (cmd_queue_empty_loc >= empty_threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1);
+ aspeed_i3c_device_update_irq(s);
+ }
+
+ return val;
+}
+
+static void aspeed_i3c_device_cmd_queue_execute(AspeedI3CDevice *s)
+{
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_IDLE);
+ if (!aspeed_i3c_device_can_transmit(s)) {
+ return;
+ }
+
+ /*
+ * We only start executing when a command is passed into the FIFO.
+ * We expect there to be a multiple of 2 items in the queue. The first item
+ * should be an argument to a command, and the command should be the second
+ * item.
+ */
+ if (fifo32_num_used(&s->cmd_queue) & 1) {
+ return;
+ }
+
+ while (!fifo32_is_empty(&s->cmd_queue)) {
+ AspeedI3CCmdQueueData arg;
+ arg.word = aspeed_i3c_device_cmd_queue_pop(s);
+ AspeedI3CCmdQueueData cmd;
+ cmd.word = aspeed_i3c_device_cmd_queue_pop(s);
+ trace_aspeed_i3c_device_cmd_queue_execute(s->id, cmd.word, arg.word);
+
+ uint8_t cmd_attr = FIELD_EX32(cmd.word, COMMAND_QUEUE_PORT, CMD_ATTR);
+ switch (cmd_attr) {
+ case ASPEED_I3C_CMD_ATTR_TRANSFER_CMD:
+ aspeed_i3c_device_transfer_cmd(s, cmd.transfer_cmd, arg);
+ break;
+ case ASPEED_I3C_CMD_ATTR_ADDR_ASSIGN_CMD:
+ /* Arg is discarded for addr assign commands. */
+ aspeed_i3c_device_addr_assign_cmd(s, cmd.addr_assign_cmd);
+ break;
+ case ASPEED_I3C_CMD_ATTR_TRANSFER_ARG:
+ case ASPEED_I3C_CMD_ATTR_SHORT_DATA_ARG:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received argument"
+ " packet when it expected a command packet\n",
+ object_get_canonical_path(OBJECT(s)));
+ break;
+ default:
+ /*
+ * The caller's check before queueing an item should prevent this
+ * from happening.
+ */
+ g_assert_not_reached();
+ break;
+ }
+ }
+}
+
+static void aspeed_i3c_device_cmd_queue_push(AspeedI3CDevice *s, uint32_t val)
+{
+ if (fifo32_is_full(&s->cmd_queue)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet when "
+ "already full\n", object_get_canonical_path(OBJECT(s)));
+ return;
+ }
+ trace_aspeed_i3c_device_cmd_queue_push(s->id, val);
+ fifo32_push(&s->cmd_queue, val);
+
+ uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ CMD_BUF_EMPTY_THLD);
+ uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs,
+ QUEUE_STATUS_LEVEL,
+ CMD_QUEUE_EMPTY_LOC);
+ if (cmd_queue_empty_loc) {
+ cmd_queue_empty_loc--;
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,
+ cmd_queue_empty_loc);
+ }
+ if (cmd_queue_empty_loc < empty_threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 0);
+ aspeed_i3c_device_update_irq(s);
+ }
+}
+
+static void aspeed_i3c_device_cmd_queue_port_w(AspeedI3CDevice *s, uint32_t val)
+{
+ uint8_t cmd_attr = FIELD_EX32(val, COMMAND_QUEUE_PORT, CMD_ATTR);
+
+ switch (cmd_attr) {
+ /* If a command is received we can start executing it. */
+ case ASPEED_I3C_CMD_ATTR_TRANSFER_CMD:
+ case ASPEED_I3C_CMD_ATTR_ADDR_ASSIGN_CMD:
+ aspeed_i3c_device_cmd_queue_push(s, val);
+ aspeed_i3c_device_cmd_queue_execute(s);
+ break;
+ /* If we get an argument just push it. */
+ case ASPEED_I3C_CMD_ATTR_TRANSFER_ARG:
+ case ASPEED_I3C_CMD_ATTR_SHORT_DATA_ARG:
+ aspeed_i3c_device_cmd_queue_push(s, val);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet with "
+ "unknown cmd attr 0x%x\n",
+ object_get_canonical_path(OBJECT(s)), cmd_attr);
+ break;
+ }
+}
+
static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
@@ -512,6 +1349,10 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
__func__, offset, value);
break;
case R_RX_TX_DATA_PORT:
+ aspeed_i3c_device_push_tx(s, val32);
+ break;
+ case R_COMMAND_QUEUE_PORT:
+ aspeed_i3c_device_cmd_queue_port_w(s, val32);
break;
case R_RESET_CTRL:
break;
@@ -566,6 +1407,13 @@ static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops,
s, name, ASPEED_I3C_DEVICE_NR_REGS << 2);
+
+ fifo32_create(&s->cmd_queue, ASPEED_I3C_CMD_QUEUE_CAPACITY);
+ fifo32_create(&s->resp_queue, ASPEED_I3C_RESP_QUEUE_CAPACITY);
+ fifo32_create(&s->tx_queue, ASPEED_I3C_TX_QUEUE_CAPACITY);
+ fifo32_create(&s->rx_queue, ASPEED_I3C_RX_QUEUE_CAPACITY);
+
+ s->bus = i3c_init_bus(DEVICE(s), name);
}
static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size)
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
index cdf7cb07f6..370c08ea45 100644
--- a/hw/i3c/trace-events
+++ b/hw/i3c/trace-events
@@ -5,6 +5,16 @@ aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 "
aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
+aspeed_i3c_device_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 " bytes to bus"
+aspeed_i3c_device_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus"
+aspeed_i3c_device_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO"
+aspeed_i3c_device_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue"
+aspeed_i3c_device_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO"
+aspeed_i3c_device_pop_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from TX FIFO"
+aspeed_i3c_device_push_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to RX FIFO"
+aspeed_i3c_device_transfer_ccc(uint32_t deviceid, uint8_t ccc) "I3C Dev[%u] transfer CCC 0x%" PRIx8
+aspeed_i3c_device_cmd_queue_execute(uint32_t deviceid, uint32_t cmd, uint32_t arg) "I3C Dev[%u] execute command 0x%" PRIx32 " arg 0x%" PRIx32
+aspeed_i3c_device_cmd_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to cmd queue"
# core.c
i3c_target_event(uint8_t address, uint8_t event) "I3C target 0x%" PRIx8 " event 0x%" PRIx8
diff --git a/include/hw/i3c/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h
index 39679dfa1a..55f2f45915 100644
--- a/include/hw/i3c/aspeed_i3c.h
+++ b/include/hw/i3c/aspeed_i3c.h
@@ -2,6 +2,7 @@
* ASPEED I3C Controller
*
* Copyright (C) 2021 ASPEED Technology Inc.
+ * Copyright (C) 2023 Google, LLC
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
@@ -10,6 +11,8 @@
#ifndef ASPEED_I3C_H
#define ASPEED_I3C_H
+#include "qemu/fifo32.h"
+#include "hw/i3c/i3c.h"
#include "hw/sysbus.h"
#define TYPE_ASPEED_I3C "aspeed.i3c"
@@ -20,6 +23,129 @@ OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C)
#define ASPEED_I3C_DEVICE_NR_REGS (0x300 >> 2)
#define ASPEED_I3C_NR_DEVICES 6
+#define ASPEED_I3C_CMD_QUEUE_CAPACITY 0x10
+#define ASPEED_I3C_RESP_QUEUE_CAPACITY 0x10
+#define ASPEED_I3C_TX_QUEUE_CAPACITY 0x40
+#define ASPEED_I3C_RX_QUEUE_CAPACITY 0x40
+
+/* From datasheet. */
+#define ASPEED_I3C_CMD_ATTR_TRANSFER_CMD 0
+#define ASPEED_I3C_CMD_ATTR_TRANSFER_ARG 1
+#define ASPEED_I3C_CMD_ATTR_SHORT_DATA_ARG 2
+#define ASPEED_I3C_CMD_ATTR_ADDR_ASSIGN_CMD 3
+
+/* Enum values from datasheet. */
+typedef enum AspeedI3CRespQueueErr {
+ ASPEED_I3C_RESP_QUEUE_ERR_NONE = 0,
+ ASPEED_I3C_RESP_QUEUE_ERR_CRC = 1,
+ ASPEED_I3C_RESP_QUEUE_ERR_PARITY = 2,
+ ASPEED_I3C_RESP_QUEUE_ERR_FRAME = 3,
+ ASPEED_I3C_RESP_QUEUE_ERR_BROADCAST_NACK = 4,
+ ASPEED_I3C_RESP_QUEUE_ERR_DAA_NACK = 5,
+ ASPEED_I3C_RESP_QUEUE_ERR_OVERFLOW = 6,
+ ASPEED_I3C_RESP_QUEUE_ERR_ABORTED = 8,
+ ASPEED_I3C_RESP_QUEUE_ERR_I2C_NACK = 9,
+} AspeedI3CRespQueueErr;
+
+typedef enum AspeedI3CTransferState {
+ ASPEED_I3C_TRANSFER_STATE_IDLE = 0x00,
+ ASPEED_I3C_TRANSFER_STATE_START = 0x01,
+ ASPEED_I3C_TRANSFER_STATE_RESTART = 0x02,
+ ASPEED_I3C_TRANSFER_STATE_STOP = 0x03,
+ ASPEED_I3C_TRANSFER_STATE_START_HOLD = 0x04,
+ ASPEED_I3C_TRANSFER_STATE_BROADCAST_W = 0x05,
+ ASPEED_I3C_TRANSFER_STATE_BROADCAST_R = 0x06,
+ ASPEED_I3C_TRANSFER_STATE_DAA = 0x07,
+ ASPEED_I3C_TRANSFER_STATE_DAA_GEN = 0x08,
+ ASPEED_I3C_TRANSFER_STATE_CCC_BYTE = 0x0b,
+ ASPEED_I3C_TRANSFER_STATE_HDR_CMD = 0x0c,
+ ASPEED_I3C_TRANSFER_STATE_WRITE = 0x0d,
+ ASPEED_I3C_TRANSFER_STATE_READ = 0x0e,
+ ASPEED_I3C_TRANSFER_STATE_IBI_READ = 0x0f,
+ ASPEED_I3C_TRANSFER_STATE_IBI_DIS = 0x10,
+ ASPEED_I3C_TRANSFER_STATE_HDR_DDR_CRC = 0x11,
+ ASPEED_I3C_TRANSFER_STATE_CLK_STRETCH = 0x12,
+ ASPEED_I3C_TRANSFER_STATE_HALT = 0x13,
+} AspeedI3CTransferState;
+
+typedef enum AspeedI3CTransferStatus {
+ ASPEED_I3C_TRANSFER_STATUS_IDLE = 0x00,
+ ASPEED_I3C_TRANSFER_STATUS_BROACAST_CCC = 0x01,
+ ASPEED_I3C_TRANSFER_STATUS_DIRECT_CCC_W = 0x02,
+ ASPEED_I3C_TRANSFER_STATUS_DIRECT_CCC_R = 0x03,
+ ASPEED_I3C_TRANSFER_STATUS_ENTDAA = 0x04,
+ ASPEED_I3C_TRANSFER_STATUS_SETDASA = 0x05,
+ ASPEED_I3C_TRANSFER_STATUS_I3C_SDR_W = 0x06,
+ ASPEED_I3C_TRANSFER_STATUS_I3C_SDR_R = 0x07,
+ ASPEED_I3C_TRANSFER_STATUS_I2C_SDR_W = 0x08,
+ ASPEED_I3C_TRANSFER_STATUS_I2C_SDR_R = 0x09,
+ ASPEED_I3C_TRANSFER_STATUS_HDR_TS_W = 0x0a,
+ ASPEED_I3C_TRANSFER_STATUS_HDR_TS_R = 0x0b,
+ ASPEED_I3C_TRANSFER_STATUS_HDR_DDR_W = 0x0c,
+ ASPEED_I3C_TRANSFER_STATUS_HDR_DDR_R = 0x0d,
+ ASPEED_I3C_TRANSFER_STATUS_IBI = 0x0e,
+ ASPEED_I3C_TRANSFER_STATUS_HALT = 0x0f,
+} AspeedI3CTransferStatus;
+
+/*
+ * Transfer commands and arguments are 32-bit wide values that the user passes
+ * into the command queue. We interpret each 32-bit word based on the cmd_attr
+ * field.
+ */
+typedef struct AspeedI3CTransferCmd {
+ uint8_t cmd_attr:3;
+ uint8_t tid:4; /* Transaction ID */
+ uint16_t cmd:8;
+ uint8_t cp:1; /* Command present */
+ uint8_t dev_index:5;
+ uint8_t speed:3;
+ uint8_t resv0:1;
+ uint8_t dbp:1; /* Defining byte present */
+ uint8_t roc:1; /* Response on completion */
+ uint8_t sdap:1; /* Short data argument present */
+ uint8_t rnw:1; /* Read not write */
+ uint8_t resv1:1;
+ uint8_t toc:1; /* Termination (I3C STOP) on completion */
+ uint8_t pec:1; /* Parity error check enabled */
+} AspeedI3CTransferCmd;
+
+typedef struct AspeedI3CTransferArg {
+ uint8_t cmd_attr:3;
+ uint8_t resv:5;
+ uint8_t db; /* Defining byte */
+ uint16_t data_len;
+} AspeedI3CTransferArg;
+
+typedef struct AspeedI3CShortArg {
+ uint8_t cmd_attr:3;
+ uint8_t byte_strb:3;
+ uint8_t resv:2;
+ uint8_t byte0;
+ uint8_t byte1;
+ uint8_t byte2;
+} AspeedI3CShortArg;
+
+typedef struct AspeedI3CAddrAssignCmd {
+ uint8_t cmd_attr:3;
+ uint8_t tid:4; /* Transaction ID */
+ uint16_t cmd:8;
+ uint8_t resv0:1;
+ uint8_t dev_index:5;
+ uint16_t dev_count:5;
+ uint8_t roc:1; /* Response on completion */
+ uint8_t resv1:3;
+ uint8_t toc:1; /* Termination (I3C STOP) on completion */
+ uint8_t resv2:1;
+} AspeedI3CAddrAssignCmd;
+
+typedef union AspeedI3CCmdQueueData {
+ uint32_t word;
+ AspeedI3CTransferCmd transfer_cmd;
+ AspeedI3CTransferArg transfer_arg;
+ AspeedI3CShortArg short_arg;
+ AspeedI3CAddrAssignCmd addr_assign_cmd;
+} AspeedI3CCmdQueueData;
+
OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE)
typedef struct AspeedI3CDevice {
/* <private> */
@@ -28,6 +154,12 @@ typedef struct AspeedI3CDevice {
/* <public> */
MemoryRegion mr;
qemu_irq irq;
+ I3CBus *bus;
+
+ Fifo32 cmd_queue;
+ Fifo32 resp_queue;
+ Fifo32 tx_queue;
+ Fifo32 rx_queue;
uint8_t id;
uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS];
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 09/16] hw/i3c/aspeed_i3c: Add data TX and RX
2023-03-31 1:01 ` [PATCH 09/16] hw/i3c/aspeed_i3c: Add data TX and RX Joe Komlodi
@ 2023-04-03 8:45 ` Jeremy Kerr
0 siblings, 0 replies; 30+ messages in thread
From: Jeremy Kerr @ 2023-04-03 8:45 UTC (permalink / raw)
To: Joe Komlodi, qemu-devel; +Cc: venture, peter.maydell
Hi Joe,
> +static uint8_t aspeed_i3c_device_target_addr(AspeedI3CDevice *s,
> + uint16_t offset)
> +{
> + if (offset > ASPEED_I3C_NR_DEVICES) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Device addr table offset %d out of "
> + "bounds\n", object_get_canonical_path(OBJECT(s)), offset);
> + /* If we're out of bounds, return an address of 0. */
> + return 0;
> + }
> +
> + uint16_t dev_index = R_DEVICE_ADDR_TABLE_LOC1 + offset;
> + /* I2C devices use a static address. */
> + if (aspeed_i3c_device_target_is_i2c(s, offset)) {
> + return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1,
> + DEV_STATIC_ADDR);
> + }
> + return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1,
> + DEV_DYNAMIC_ADDR);
> +}
Depending on the usage of this function, you'll probably want to mask
out the parity bit (the msb) from the DEV_DYNAMIC_ADDR field.
Currently, you're returning this value directly from the ENTDAA handler,
which is ending up assigning addresses with the high bit set.
(doing a bit of a piecemeal review here, as I'm testing out the
model...)
Cheers,
Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (8 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 09/16] hw/i3c/aspeed_i3c: Add data TX and RX Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-04-03 3:08 ` Jeremy Kerr
2023-04-11 9:16 ` Jeremy Kerr
2023-03-31 1:01 ` [PATCH 11/16] hw/i3c/aspeed_i3c: Add ctrl MMIO handling Joe Komlodi
` (6 subsequent siblings)
16 siblings, 2 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds handling for different IBI events that the controller can receive.
This includes:
- Handling a hot-join from a target
- Handling a secondary controller on the bus requesting to be the
primary bus controller
- Handling an interrupt request from a target.
When receiving an IBI, the controller sets an interrupt to notify
software about what happened.
When the IBI is finished being serviced, the controller pushes the
result of the IBI and any data received from the target into the IBI
queue.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
---
hw/i3c/aspeed_i3c.c | 310 ++++++++++++++++++++++++++++++++++++
hw/i3c/trace-events | 2 +
include/hw/i3c/aspeed_i3c.h | 27 ++++
3 files changed, 339 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index ffe0b21ca0..055ad3f7fd 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -20,6 +20,14 @@
#include "hw/i3c/i3c.h"
#include "hw/irq.h"
+/*
+ * Disable event command values. sent along with a DISEC CCC to disable certain
+ * events on targets.
+ */
+#define DISEC_HJ 0x08
+#define DISEC_CR 0x02
+#define DISEC_INT 0x01
+
/* I3C Controller Registers */
REG32(I3C1_REG0, 0x10)
REG32(I3C1_REG1, 0x14)
@@ -444,6 +452,23 @@ static inline uint8_t aspeed_i3c_device_fifo_threshold_from_reg(uint8_t regval)
return regval = regval ? (2 << regval) : 1;
}
+static inline uint8_t aspeed_i3c_device_ibi_slice_size(AspeedI3CDevice *s)
+{
+ uint8_t ibi_slice_size = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ IBI_DATA_THLD);
+ /* The minimum supported slice size is 4 bytes. */
+ if (ibi_slice_size == 0) {
+ ibi_slice_size = 1;
+ }
+ ibi_slice_size *= sizeof(uint32_t);
+ /* maximum supported size is 63 bytes. */
+ if (ibi_slice_size >= 64) {
+ ibi_slice_size = 63;
+ }
+
+ return ibi_slice_size;
+}
+
static void aspeed_i3c_device_update_irq(AspeedI3CDevice *s)
{
bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]);
@@ -591,6 +616,261 @@ static uint8_t aspeed_i3c_device_target_addr(AspeedI3CDevice *s,
DEV_DYNAMIC_ADDR);
}
+static int aspeed_i3c_device_addr_table_index_from_addr(AspeedI3CDevice *s,
+ uint8_t addr)
+{
+ uint8_t table_size = ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER,
+ DEPTH);
+ for (uint8_t i = 0; i < table_size; i++) {
+ if (aspeed_i3c_device_target_addr(s, i) == addr) {
+ return i;
+ }
+ }
+ return -1;
+}
+
+static void aspeed_i3c_device_send_disec(AspeedI3CDevice *s)
+{
+ uint8_t ccc = I3C_CCC_DISEC;
+ if (s->ibi_data.send_direct_disec) {
+ ccc = I3C_CCCD_DISEC;
+ }
+
+ aspeed_i3c_device_send_start(s, I3C_BROADCAST, /*is_recv=*/false,
+ /*is_i2c=*/false);
+ aspeed_i3c_device_send_byte(s, ccc, /*is_i2c=*/false);
+ if (s->ibi_data.send_direct_disec) {
+ aspeed_i3c_device_send_start(s, s->ibi_data.disec_addr,
+ /*is_recv=*/false, /*is_i2c=*/false);
+ }
+ aspeed_i3c_device_send_byte(s, s->ibi_data.disec_byte, /*is_i2c=*/false);
+}
+
+static int aspeed_i3c_device_handle_hj(AspeedI3CDevice *s)
+{
+ if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN)) {
+ s->ibi_data.notify_ibi_nack = true;
+ }
+
+ bool nack_and_disable = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL,
+ HOT_JOIN_ACK_NACK_CTRL);
+ if (nack_and_disable) {
+ s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status,
+ IBI_QUEUE_STATUS,
+ IBI_STATUS, 1);
+ s->ibi_data.ibi_nacked = true;
+ s->ibi_data.disec_byte = DISEC_HJ;
+ return -1;
+ }
+ return 0;
+}
+
+static int aspeed_i3c_device_handle_ctlr_req(AspeedI3CDevice *s, uint8_t addr)
+{
+ if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ)) {
+ s->ibi_data.notify_ibi_nack = true;
+ }
+
+ int table_offset = aspeed_i3c_device_addr_table_index_from_addr(s, addr);
+ /* Doesn't exist in the table, NACK it, don't DISEC. */
+ if (table_offset < 0) {
+ return -1;
+ }
+
+ table_offset += R_DEVICE_ADDR_TABLE_LOC1;
+ if (FIELD_EX32(s->regs[table_offset], DEVICE_ADDR_TABLE_LOC1, MR_REJECT)) {
+ s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status,
+ IBI_QUEUE_STATUS,
+ IBI_STATUS, 1);
+ s->ibi_data.ibi_nacked = true;
+ s->ibi_data.disec_addr = addr;
+ /* Tell the requester to disable controller role requests. */
+ s->ibi_data.disec_byte = DISEC_CR;
+ s->ibi_data.send_direct_disec = true;
+ return -1;
+ }
+ return 0;
+}
+
+static int aspeed_i3c_device_handle_targ_irq(AspeedI3CDevice *s, uint8_t addr)
+{
+ if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ)) {
+ s->ibi_data.notify_ibi_nack = true;
+ }
+
+ int table_offset = aspeed_i3c_device_addr_table_index_from_addr(s, addr);
+ /* Doesn't exist in the table, NACK it, don't DISEC. */
+ if (table_offset < 0) {
+ return -1;
+ }
+
+ table_offset += R_DEVICE_ADDR_TABLE_LOC1;
+ if (FIELD_EX32(s->regs[table_offset], DEVICE_ADDR_TABLE_LOC1, SIR_REJECT)) {
+ s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status,
+ IBI_QUEUE_STATUS,
+ IBI_STATUS, 1);
+ s->ibi_data.ibi_nacked = true;
+ s->ibi_data.disec_addr = addr;
+ /* Tell the requester to disable interrupts. */
+ s->ibi_data.disec_byte = DISEC_INT;
+ s->ibi_data.send_direct_disec = true;
+ return -1;
+ }
+ return 0;
+}
+
+static int aspeed_i3c_device_ibi_handle(I3CBus *bus, I3CTarget *target,
+ uint8_t addr, bool is_recv)
+{
+ AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
+
+ trace_aspeed_i3c_device_ibi_handle(s->id, addr, is_recv);
+ s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status,
+ IBI_QUEUE_STATUS, IBI_ID,
+ (addr << 1) | is_recv);
+ /* Is this a hot join request? */
+ if (addr == I3C_HJ_ADDR) {
+ return aspeed_i3c_device_handle_hj(s);
+ }
+ /* Is secondary controller requesting access? */
+ if (addr == target->address && !is_recv) {
+ return aspeed_i3c_device_handle_ctlr_req(s, addr);
+ }
+ /* Is this a target IRQ? */
+ if (addr == target->address && is_recv) {
+ return aspeed_i3c_device_handle_targ_irq(s, addr);
+ }
+
+ /* Not sure what this is, NACK it. */
+ return -1;
+}
+
+static int aspeed_i3c_device_ibi_recv(I3CBus *bus, uint8_t data)
+{
+ AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
+ if (fifo8_is_full(&s->ibi_data.ibi_intermediate_queue)) {
+ return -1;
+ }
+
+ fifo8_push(&s->ibi_data.ibi_intermediate_queue, data);
+ trace_aspeed_i3c_device_ibi_recv(s->id, data);
+ return 0;
+}
+
+static void aspeed_i3c_device_ibi_queue_push(AspeedI3CDevice *s)
+{
+ /* Stored value is in 32-bit chunks, convert it to byte chunks. */
+ uint8_t ibi_slice_size = aspeed_i3c_device_ibi_slice_size(s);
+ uint8_t num_slices = fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) /
+ ibi_slice_size;
+ uint8_t ibi_status_count = num_slices;
+ union {
+ uint8_t b[sizeof(uint32_t)];
+ uint32_t val32;
+ } ibi_data = {
+ .val32 = 0
+ };
+
+ /* The report was suppressed, do nothing. */
+ if (s->ibi_data.ibi_nacked && !s->ibi_data.notify_ibi_nack) {
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_IDLE);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
+ ASPEED_I3C_TRANSFER_STATUS_IDLE);
+ return;
+ }
+
+ /* If we don't have any slices to push, just push the status. */
+ if (num_slices == 0) {
+ s->ibi_data.ibi_queue_status =
+ FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
+ LAST_STATUS, 1);
+ fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status);
+ ibi_status_count = 1;
+ }
+
+ for (uint8_t i = 0; i < num_slices; i++) {
+ /* If this is the last slice, set LAST_STATUS. */
+ if (fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) <
+ ibi_slice_size) {
+ s->ibi_data.ibi_queue_status =
+ FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
+ IBI_DATA_LEN,
+ fifo8_num_used(&s->ibi_data.ibi_intermediate_queue));
+ s->ibi_data.ibi_queue_status =
+ FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
+ LAST_STATUS, 1);
+ } else {
+ s->ibi_data.ibi_queue_status =
+ FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
+ IBI_DATA_LEN, ibi_slice_size);
+ }
+
+ /* Push the IBI status header. */
+ fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status);
+ /* Move each IBI byte into a 32-bit word and push it into the queue. */
+ for (uint8_t j = 0; j < ibi_slice_size; ++j) {
+ if (fifo8_is_empty(&s->ibi_data.ibi_intermediate_queue)) {
+ break;
+ }
+
+ ibi_data.b[j & 3] = fifo8_pop(&s->ibi_data.ibi_intermediate_queue);
+ /* We have 32-bits, push it to the IBI FIFO. */
+ if ((j & 0x03) == 0x03) {
+ fifo32_push(&s->ibi_queue, ibi_data.val32);
+ ibi_data.val32 = 0;
+ }
+ }
+ /* If the data isn't 32-bit aligned, push the leftover bytes. */
+ if (ibi_slice_size & 0x03) {
+ fifo32_push(&s->ibi_queue, ibi_data.val32);
+ }
+
+ /* Clear out the data length for the next iteration. */
+ s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status,
+ IBI_QUEUE_STATUS, IBI_DATA_LEN, 0);
+ }
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR,
+ fifo32_num_used(&s->ibi_queue));
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_STATUS_CNT,
+ ibi_status_count);
+ /* Threshold is the register value + 1. */
+ uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ IBI_STATUS_THLD) + 1;
+ if (fifo32_num_used(&s->ibi_queue) >= threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 1);
+ aspeed_i3c_device_update_irq(s);
+ }
+
+ /* State update. */
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_IDLE);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
+ ASPEED_I3C_TRANSFER_STATUS_IDLE);
+}
+
+static int aspeed_i3c_device_ibi_finish(I3CBus *bus)
+{
+ AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
+ bool nack_and_disable_hj = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL,
+ HOT_JOIN_ACK_NACK_CTRL);
+ if (nack_and_disable_hj || s->ibi_data.send_direct_disec) {
+ aspeed_i3c_device_send_disec(s);
+ }
+ aspeed_i3c_device_ibi_queue_push(s);
+
+ /* Clear out the intermediate values. */
+ s->ibi_data.ibi_queue_status = 0;
+ s->ibi_data.disec_addr = 0;
+ s->ibi_data.disec_byte = 0;
+ s->ibi_data.send_direct_disec = false;
+ s->ibi_data.notify_ibi_nack = false;
+ s->ibi_data.ibi_nacked = false;
+
+ return 0;
+}
+
static uint32_t aspeed_i3c_device_intr_status_r(AspeedI3CDevice *s)
{
/* Only return the status whose corresponding EN bits are set. */
@@ -650,6 +930,25 @@ static uint32_t aspeed_i3c_device_pop_rx(AspeedI3CDevice *s)
return val;
}
+static uint32_t aspeed_i3c_device_ibi_queue_r(AspeedI3CDevice *s)
+{
+ if (fifo32_is_empty(&s->ibi_queue)) {
+ return 0;
+ }
+
+ uint32_t val = fifo32_pop(&s->ibi_queue);
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR,
+ fifo32_num_used(&s->ibi_queue));
+ /* Threshold is the register value + 1. */
+ uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ IBI_STATUS_THLD) + 1;
+ if (fifo32_num_used(&s->ibi_queue) < threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0);
+ aspeed_i3c_device_update_irq(s);
+ }
+ return val;
+}
+
static uint32_t aspeed_i3c_device_resp_queue_port_r(AspeedI3CDevice *s)
{
if (fifo32_is_empty(&s->resp_queue)) {
@@ -687,6 +986,9 @@ static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
case R_INTR_FORCE:
value = 0;
break;
+ case R_IBI_QUEUE_DATA:
+ value = aspeed_i3c_device_ibi_queue_r(s);
+ break;
case R_INTR_STATUS:
value = aspeed_i3c_device_intr_status_r(s);
break;
@@ -1412,8 +1714,16 @@ static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp)
fifo32_create(&s->resp_queue, ASPEED_I3C_RESP_QUEUE_CAPACITY);
fifo32_create(&s->tx_queue, ASPEED_I3C_TX_QUEUE_CAPACITY);
fifo32_create(&s->rx_queue, ASPEED_I3C_RX_QUEUE_CAPACITY);
+ fifo32_create(&s->ibi_queue, ASPEED_I3C_IBI_QUEUE_CAPACITY);
+ /* Arbitrarily large enough to not be an issue. */
+ fifo8_create(&s->ibi_data.ibi_intermediate_queue,
+ ASPEED_I3C_IBI_QUEUE_CAPACITY * 8);
s->bus = i3c_init_bus(DEVICE(s), name);
+ I3CBusClass *bc = I3C_BUS_GET_CLASS(s->bus);
+ bc->ibi_handle = aspeed_i3c_device_ibi_handle;
+ bc->ibi_recv = aspeed_i3c_device_ibi_recv;
+ bc->ibi_finish = aspeed_i3c_device_ibi_finish;
}
static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size)
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
index 370c08ea45..7a202b28c9 100644
--- a/hw/i3c/trace-events
+++ b/hw/i3c/trace-events
@@ -7,6 +7,8 @@ aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C D
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 " bytes to bus"
aspeed_i3c_device_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus"
+aspeed_i3c_device_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRIx8
+aspeed_i3c_device_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI from address 0x%" PRIx8 " RnW=%d"
aspeed_i3c_device_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO"
aspeed_i3c_device_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue"
aspeed_i3c_device_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO"
diff --git a/include/hw/i3c/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h
index 55f2f45915..d2f0739b79 100644
--- a/include/hw/i3c/aspeed_i3c.h
+++ b/include/hw/i3c/aspeed_i3c.h
@@ -27,6 +27,7 @@ OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C)
#define ASPEED_I3C_RESP_QUEUE_CAPACITY 0x10
#define ASPEED_I3C_TX_QUEUE_CAPACITY 0x40
#define ASPEED_I3C_RX_QUEUE_CAPACITY 0x40
+#define ASPEED_I3C_IBI_QUEUE_CAPACITY 0x10
/* From datasheet. */
#define ASPEED_I3C_CMD_ATTR_TRANSFER_CMD 0
@@ -146,6 +147,28 @@ typedef union AspeedI3CCmdQueueData {
AspeedI3CAddrAssignCmd addr_assign_cmd;
} AspeedI3CCmdQueueData;
+/*
+ * When we receive an IBI with data, we need to store it temporarily until
+ * the target is finished sending data. Then we can set the IBI queue status
+ * appropriately.
+ */
+typedef struct AspeedI3CDeviceIBIData {
+ /* Do we notify the user that an IBI was NACKed? */
+ bool notify_ibi_nack;
+ /* Intermediate storage of IBI_QUEUE_STATUS. */
+ uint32_t ibi_queue_status;
+ /* Temporary buffer to store IBI data from the target. */
+ Fifo8 ibi_intermediate_queue;
+ /* The address we should send a CCC_DISEC to. */
+ uint8_t disec_addr;
+ /* The byte we should send along with the CCC_DISEC. */
+ uint8_t disec_byte;
+ /* Should we send a direct DISEC CCC? (As opposed to global). */
+ bool send_direct_disec;
+ /* Was this IBI NACKed? */
+ bool ibi_nacked;
+} AspeedI3CDeviceIBIData;
+
OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE)
typedef struct AspeedI3CDevice {
/* <private> */
@@ -160,6 +183,10 @@ typedef struct AspeedI3CDevice {
Fifo32 resp_queue;
Fifo32 tx_queue;
Fifo32 rx_queue;
+ Fifo32 ibi_queue;
+
+ /* Temporary storage for IBI data. */
+ AspeedI3CDeviceIBIData ibi_data;
uint8_t id;
uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS];
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling
2023-03-31 1:01 ` [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling Joe Komlodi
@ 2023-04-03 3:08 ` Jeremy Kerr
2023-04-11 9:16 ` Jeremy Kerr
1 sibling, 0 replies; 30+ messages in thread
From: Jeremy Kerr @ 2023-04-03 3:08 UTC (permalink / raw)
To: Joe Komlodi, qemu-devel; +Cc: venture, peter.maydell
Hi Joe,
First up, nice work with this series! I haven't yet had a thorough look
at the series, but one item on something that caught me up on the Linux
side:
> +static void aspeed_i3c_device_ibi_queue_push(AspeedI3CDevice *s)
> +{
> + /* Stored value is in 32-bit chunks, convert it to byte chunks. */
> + uint8_t ibi_slice_size = aspeed_i3c_device_ibi_slice_size(s);
> + uint8_t num_slices = fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) /
> + ibi_slice_size;
> + uint8_t ibi_status_count = num_slices;
> + union {
> + uint8_t b[sizeof(uint32_t)];
> + uint32_t val32;
> + } ibi_data = {
> + .val32 = 0
> + };
> +
> + /* The report was suppressed, do nothing. */
> + if (s->ibi_data.ibi_nacked && !s->ibi_data.notify_ibi_nack) {
> + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
> + ASPEED_I3C_TRANSFER_STATE_IDLE);
> + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
> + ASPEED_I3C_TRANSFER_STATUS_IDLE);
> + return;
> + }
> +
> + /* If we don't have any slices to push, just push the status. */
> + if (num_slices == 0) {
> + s->ibi_data.ibi_queue_status =
> + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
> + LAST_STATUS, 1);
> + fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status);
> + ibi_status_count = 1;
> + }
> +
> + for (uint8_t i = 0; i < num_slices; i++) {
> + /* If this is the last slice, set LAST_STATUS. */
> + if (fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) <
> + ibi_slice_size) {
> + s->ibi_data.ibi_queue_status =
> + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
> + IBI_DATA_LEN,
> + fifo8_num_used(&s->ibi_data.ibi_intermediate_queue));
> + s->ibi_data.ibi_queue_status =
> + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
> + LAST_STATUS, 1);
> + } else {
> + s->ibi_data.ibi_queue_status =
> + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS,
> + IBI_DATA_LEN, ibi_slice_size);
> + }
> +
> + /* Push the IBI status header. */
> + fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status);
> + /* Move each IBI byte into a 32-bit word and push it into the queue. */
> + for (uint8_t j = 0; j < ibi_slice_size; ++j) {
> + if (fifo8_is_empty(&s->ibi_data.ibi_intermediate_queue)) {
> + break;
> + }
> +
> + ibi_data.b[j & 3] = fifo8_pop(&s->ibi_data.ibi_intermediate_queue);
> + /* We have 32-bits, push it to the IBI FIFO. */
> + if ((j & 0x03) == 0x03) {
> + fifo32_push(&s->ibi_queue, ibi_data.val32);
> + ibi_data.val32 = 0;
> + }
> + }
You'll probably want to handle the IBI_PEC_EN DAT field when pushing the
IBI to the fifo here.
Due to a HW errata, the driver will *always* need to enable PEC_EN. In
cases where the remote isn't actually sending a PEC, this will consume
the last byte of the IBI payload (and probably cause a PEC error, which
the driver needs to ignore).
See here for the driver side, in patches 4/5 and 5/5:
https://lore.kernel.org/linux-i3c/d5d76a8d2336d2a71886537f42e71d51db184df6.1680161823.git.jk@codeconstruct.com.au/T/#u
Cheers,
Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling
2023-03-31 1:01 ` [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling Joe Komlodi
2023-04-03 3:08 ` Jeremy Kerr
@ 2023-04-11 9:16 ` Jeremy Kerr
2023-04-12 23:13 ` Joe Komlodi
1 sibling, 1 reply; 30+ messages in thread
From: Jeremy Kerr @ 2023-04-11 9:16 UTC (permalink / raw)
To: Joe Komlodi, qemu-devel; +Cc: venture, peter.maydell
Hi Joe,
> +static int aspeed_i3c_device_ibi_finish(I3CBus *bus)
> +{
> + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
> + bool nack_and_disable_hj = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL,
> + HOT_JOIN_ACK_NACK_CTRL);
> + if (nack_and_disable_hj || s->ibi_data.send_direct_disec) {
> + aspeed_i3c_device_send_disec(s);
> + }
Shouldn't this be conditional on the ibi being a HJ request? With this,
I'm seeing the DISEC happen on *all* IBIs.
Cheers,
Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling
2023-04-11 9:16 ` Jeremy Kerr
@ 2023-04-12 23:13 ` Joe Komlodi
0 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-04-12 23:13 UTC (permalink / raw)
To: Jeremy Kerr; +Cc: qemu-devel, venture, peter.maydell
Hi jeremy,
On Tue, Apr 11, 2023 at 2:17 AM Jeremy Kerr <jk@codeconstruct.com.au> wrote:
>
> Hi Joe,
>
> > +static int aspeed_i3c_device_ibi_finish(I3CBus *bus)
> > +{
> > + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
> > + bool nack_and_disable_hj = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL,
> > + HOT_JOIN_ACK_NACK_CTRL);
> > + if (nack_and_disable_hj || s->ibi_data.send_direct_disec) {
> > + aspeed_i3c_device_send_disec(s);
> > + }
>
> Shouldn't this be conditional on the ibi being a HJ request? With this,
> I'm seeing the DISEC happen on *all* IBIs.
Good catch! Yep it should be on HJs only.
Will fix in v2 as well.
Thanks,
Joe
>
> Cheers,
>
>
> Jeremy
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 11/16] hw/i3c/aspeed_i3c: Add ctrl MMIO handling
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (9 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 10/16] hw/i3c/aspeed_i3c: Add IBI handling Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 12/16] hw/i3c/aspeed_i3c: Add controller resets Joe Komlodi
` (5 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds functionality to the CTRL register.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/aspeed_i3c.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 055ad3f7fd..4c0c074012 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -340,6 +340,8 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2)
FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
+static void aspeed_i3c_device_cmd_queue_execute(AspeedI3CDevice *s);
+
static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_I3C1_REG0] = 0xfc000000,
[R_I3C1_REG1] = 0xfff00000,
@@ -588,6 +590,37 @@ static int aspeed_i3c_device_recv_data(AspeedI3CDevice *s, bool is_i2c,
return ret;
}
+static inline void aspeed_i3c_device_ctrl_w(AspeedI3CDevice *s,
+ uint32_t val)
+{
+ /*
+ * If the user is setting I3C_RESUME, the controller was halted.
+ * Try and resume execution and leave the bit cleared.
+ */
+ if (FIELD_EX32(val, DEVICE_CTRL, I3C_RESUME)) {
+ aspeed_i3c_device_cmd_queue_execute(s);
+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 0);
+ }
+ /*
+ * I3C_ABORT being set sends an I3C STOP. It's cleared when the STOP is
+ * sent.
+ */
+ if (FIELD_EX32(val, DEVICE_CTRL, I3C_ABORT)) {
+ aspeed_i3c_device_end_transfer(s, /*is_i2c=*/true);
+ aspeed_i3c_device_end_transfer(s, /*is_i2c=*/false);
+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_ABORT, 0);
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ABORT, 1);
+ aspeed_i3c_device_update_irq(s);
+ }
+ /* Update present state. */
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
+ ASPEED_I3C_TRANSFER_STATE_IDLE);
+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
+ ASPEED_I3C_TRANSFER_STATUS_IDLE);
+
+ s->regs[R_DEVICE_CTRL] = val;
+}
+
static inline bool aspeed_i3c_device_target_is_i2c(AspeedI3CDevice *s,
uint16_t offset)
{
@@ -1650,6 +1683,9 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
"] = 0x%08" PRIx64 "\n",
__func__, offset, value);
break;
+ case R_DEVICE_CTRL:
+ aspeed_i3c_device_ctrl_w(s, val32);
+ break;
case R_RX_TX_DATA_PORT:
aspeed_i3c_device_push_tx(s, val32);
break;
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 12/16] hw/i3c/aspeed_i3c: Add controller resets
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (10 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 11/16] hw/i3c/aspeed_i3c: Add ctrl MMIO handling Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 13/16] hw/i3c: Add Mock target Joe Komlodi
` (4 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds behavior to the device reset register.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
---
hw/i3c/aspeed_i3c.c | 110 +++++++++++++++++++++++++++++++++++++++++---
hw/i3c/trace-events | 1 +
2 files changed, 104 insertions(+), 7 deletions(-)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 4c0c074012..19d766f074 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -938,6 +938,108 @@ static void aspeed_i3c_device_intr_force_w(AspeedI3CDevice *s, uint32_t val)
aspeed_i3c_device_update_irq(s);
}
+static void aspeed_i3c_device_cmd_queue_reset(AspeedI3CDevice *s)
+{
+ fifo32_reset(&s->cmd_queue);
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,
+ fifo32_num_free(&s->cmd_queue));
+ uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ CMD_BUF_EMPTY_THLD);
+ if (fifo32_num_free(&s->cmd_queue) >= empty_threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1);
+ aspeed_i3c_device_update_irq(s);
+ };
+}
+
+static void aspeed_i3c_device_resp_queue_reset(AspeedI3CDevice *s)
+{
+ fifo32_reset(&s->resp_queue);
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+ /*
+ * This interrupt will always be cleared because the threshold is a minimum
+ * of 1 and the queue size is 0.
+ */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0);
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_ibi_queue_reset(AspeedI3CDevice *s)
+{
+ fifo32_reset(&s->ibi_queue);
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+ /*
+ * This interrupt will always be cleared because the threshold is a minimum
+ * of 1 and the queue size is 0.
+ */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0);
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_tx_queue_reset(AspeedI3CDevice *s)
+{
+ fifo32_reset(&s->tx_queue);
+
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,
+ fifo32_num_free(&s->tx_queue));
+ /* TX buf is empty, so this interrupt will always be set. */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1);
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_rx_queue_reset(AspeedI3CDevice *s)
+{
+ fifo32_reset(&s->rx_queue);
+
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+ /*
+ * This interrupt will always be cleared because the threshold is a minimum
+ * of 1 and the queue size is 0.
+ */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0);
+ aspeed_i3c_device_update_irq(s);
+}
+
+static void aspeed_i3c_device_reset(DeviceState *dev)
+{
+ AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev);
+ trace_aspeed_i3c_device_reset(s->id);
+
+ memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs));
+ aspeed_i3c_device_cmd_queue_reset(s);
+ aspeed_i3c_device_resp_queue_reset(s);
+ aspeed_i3c_device_ibi_queue_reset(s);
+ aspeed_i3c_device_tx_queue_reset(s);
+ aspeed_i3c_device_rx_queue_reset(s);
+}
+
+static void aspeed_i3c_device_reset_ctrl_w(AspeedI3CDevice *s, uint32_t val)
+{
+ if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) {
+ aspeed_i3c_device_reset(DEVICE(s));
+ }
+ if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) {
+ aspeed_i3c_device_cmd_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) {
+ aspeed_i3c_device_resp_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, TX_BUF_RESET)) {
+ aspeed_i3c_device_tx_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, RX_BUF_RESET)) {
+ aspeed_i3c_device_rx_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, IBI_QUEUE_RESET)) {
+ aspeed_i3c_device_ibi_queue_reset(s);
+ }
+}
+
static uint32_t aspeed_i3c_device_pop_rx(AspeedI3CDevice *s)
{
if (fifo32_is_empty(&s->rx_queue)) {
@@ -1693,6 +1795,7 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
aspeed_i3c_device_cmd_queue_port_w(s, val32);
break;
case R_RESET_CTRL:
+ aspeed_i3c_device_reset_ctrl_w(s, val32);
break;
case R_INTR_STATUS:
aspeed_i3c_device_intr_status_w(s, val32);
@@ -1728,13 +1831,6 @@ static const MemoryRegionOps aspeed_i3c_device_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void aspeed_i3c_device_reset(DeviceState *dev)
-{
- AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev);
-
- memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs));
-}
-
static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp)
{
AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev);
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
index 7a202b28c9..71e3059f8d 100644
--- a/hw/i3c/trace-events
+++ b/hw/i3c/trace-events
@@ -9,6 +9,7 @@ aspeed_i3c_device_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send
aspeed_i3c_device_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus"
aspeed_i3c_device_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRIx8
aspeed_i3c_device_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI from address 0x%" PRIx8 " RnW=%d"
+aspeed_i3c_device_reset(uint32_t deviceid) "I3C Dev[%u] reset"
aspeed_i3c_device_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO"
aspeed_i3c_device_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue"
aspeed_i3c_device_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO"
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 13/16] hw/i3c: Add Mock target
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (11 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 12/16] hw/i3c/aspeed_i3c: Add controller resets Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 14/16] hw/i3c: remote_i3c: Add model Joe Komlodi
` (3 subsequent siblings)
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds a simple i3c device to be used for testing in lieu of a real
device.
The mock target supports the following features:
- A buffer that users can read and write to.
- CCC support for commonly used CCCs when probing devices on an I3C bus.
- IBI sending upon receiving a user-defined byte.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/Kconfig | 10 ++
hw/i3c/meson.build | 1 +
hw/i3c/mock-target.c | 312 +++++++++++++++++++++++++++++++++++
hw/i3c/trace-events | 9 +
include/hw/i3c/mock-target.h | 60 +++++++
5 files changed, 392 insertions(+)
create mode 100644 hw/i3c/mock-target.c
create mode 100644 include/hw/i3c/mock-target.h
diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig
index e07fe445c6..f97f4066a9 100644
--- a/hw/i3c/Kconfig
+++ b/hw/i3c/Kconfig
@@ -1,2 +1,12 @@
config I3C
bool
+
+config I3C_DEVICES
+ # Device group for i3c devices which can reasonably be user-plugged to any
+ # board's i3c bus.
+ bool
+
+config MOCK_TARGET
+ bool
+ select I3C
+ default y if I3C_DEVICES
diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build
index 3599f1a396..0f6268063e 100644
--- a/hw/i3c/meson.build
+++ b/hw/i3c/meson.build
@@ -1,4 +1,5 @@
i3c_ss = ss.source_set()
i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c'))
i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c'))
+i3c_ss.add(when: 'CONFIG_MOCK_TARGET', if_true: files('mock-target.c'))
softmmu_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss)
diff --git a/hw/i3c/mock-target.c b/hw/i3c/mock-target.c
new file mode 100644
index 0000000000..388d21d5ca
--- /dev/null
+++ b/hw/i3c/mock-target.c
@@ -0,0 +1,312 @@
+/*
+ * Mock I3C Device
+ *
+ * Copyright (c) 2023 Google LLC
+ *
+ * The mock I3C device can be thought of as a simple EEPROM. It has a buffer,
+ * and the pointer in the buffer is reset to 0 on an I3C STOP.
+ * To write to the buffer, issue a private write and send data.
+ * To read from the buffer, issue a private read.
+ *
+ * The mock target also supports sending target interrupt IBIs.
+ * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number, and
+ * send that number in a private transaction. The mock target will issue an IBI
+ * after 1 second.
+ *
+ * It also supports a handful of CCCs that are typically used when probing I3C
+ * devices.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/i3c/i3c.h"
+#include "hw/i3c/mock-target.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+
+#ifndef MOCK_TARGET_DEBUG
+#define MOCK_TARGET_DEBUG 0
+#endif
+
+#define DB_PRINTF(...) do { \
+ if (MOCK_TARGET_DEBUG) { \
+ qemu_log("%s: ", __func__); \
+ qemu_log(__VA_ARGS__); \
+ } \
+ } while (0)
+
+#define IBI_DELAY_NS (1 * 1000 * 1000)
+
+static uint32_t mock_target_rx(I3CTarget *i3c, uint8_t *data,
+ uint32_t num_to_read)
+{
+ MockTargetState *s = MOCK_TARGET(i3c);
+ uint32_t i;
+
+ /* Bounds check. */
+ if (s->p_buf == s->cfg.buf_size) {
+ return 0;
+ }
+
+ for (i = 0; i < num_to_read; i++) {
+ data[i] = s->buf[s->p_buf];
+ trace_mock_target_rx(data[i]);
+ s->p_buf++;
+ if (s->p_buf == s->cfg.buf_size) {
+ break;
+ }
+ }
+
+ /* Return the number of bytes we're sending to the controller. */
+ return i;
+}
+
+static void mock_target_ibi_timer_start(MockTargetState *s)
+{
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ timer_mod(&s->qtimer, now + IBI_DELAY_NS);
+}
+
+static int mock_target_tx(I3CTarget *i3c, const uint8_t *data,
+ uint32_t num_to_send, uint32_t *num_sent)
+{
+ MockTargetState *s = MOCK_TARGET(i3c);
+ int ret;
+ uint32_t to_write;
+
+ if (s->cfg.ibi_magic && num_to_send == 1 && s->cfg.ibi_magic == *data) {
+ mock_target_ibi_timer_start(s);
+ return 0;
+ }
+
+ /* Bounds check. */
+ if (num_to_send + s->p_buf > s->cfg.buf_size) {
+ to_write = s->cfg.buf_size - s->p_buf;
+ ret = -1;
+ } else {
+ to_write = num_to_send;
+ ret = 0;
+ }
+ for (uint32_t i = 0; i < to_write; i++) {
+ trace_mock_target_tx(data[i]);
+ s->buf[s->p_buf] = data[i];
+ s->p_buf++;
+ }
+ return ret;
+}
+
+static int mock_target_event(I3CTarget *i3c, enum I3CEvent event)
+{
+ MockTargetState *s = MOCK_TARGET(i3c);
+
+ trace_mock_target_event(event);
+ if (event == I3C_STOP) {
+ s->in_ccc = false;
+ s->curr_ccc = 0;
+ s->ccc_byte_offset = 0;
+ s->p_buf = 0;
+ }
+
+ return 0;
+}
+
+static int mock_target_handle_ccc_read(I3CTarget *i3c, uint8_t *data,
+ uint32_t num_to_read, uint32_t *num_read)
+{
+ MockTargetState *s = MOCK_TARGET(i3c);
+
+ switch (s->curr_ccc) {
+ case I3C_CCCD_GETMXDS:
+ /* Default data rate for I3C. */
+ while (s->ccc_byte_offset < num_to_read) {
+ if (s->ccc_byte_offset >= 2) {
+ break;
+ }
+ data[s->ccc_byte_offset] = 0;
+ *num_read = s->ccc_byte_offset;
+ s->ccc_byte_offset++;
+ }
+ break;
+ case I3C_CCCD_GETCAPS:
+ /* Support I3C version 1.1.x, no other features. */
+ while (s->ccc_byte_offset < num_to_read) {
+ if (s->ccc_byte_offset >= 2) {
+ break;
+ }
+ if (s->ccc_byte_offset == 0) {
+ data[s->ccc_byte_offset] = 0;
+ } else {
+ data[s->ccc_byte_offset] = 0x01;
+ }
+ *num_read = s->ccc_byte_offset;
+ s->ccc_byte_offset++;
+ }
+ break;
+ case I3C_CCCD_GETMWL:
+ case I3C_CCCD_GETMRL:
+ /* MWL/MRL is MSB first. */
+ while (s->ccc_byte_offset < num_to_read) {
+ if (s->ccc_byte_offset >= 2) {
+ break;
+ }
+ data[s->ccc_byte_offset] = (s->cfg.buf_size &
+ (0xff00 >> (s->ccc_byte_offset * 8))) >>
+ (8 - (s->ccc_byte_offset * 8));
+ s->ccc_byte_offset++;
+ *num_read = num_to_read;
+ }
+ break;
+ case I3C_CCC_ENTDAA:
+ case I3C_CCCD_GETPID:
+ case I3C_CCCD_GETBCR:
+ case I3C_CCCD_GETDCR:
+ /* Nothing to do. */
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_ccc);
+ return -1;
+ }
+
+ trace_mock_target_handle_ccc_read(*num_read, num_to_read);
+ return 0;
+}
+
+static int mock_target_handle_ccc_write(I3CTarget *i3c, const uint8_t *data,
+ uint32_t num_to_send,
+ uint32_t *num_sent)
+{
+ MockTargetState *s = MOCK_TARGET(i3c);
+
+ if (!s->curr_ccc) {
+ s->in_ccc = true;
+ s->curr_ccc = *data;
+ trace_mock_target_new_ccc(s->curr_ccc);
+ }
+
+ *num_sent = 1;
+ switch (s->curr_ccc) {
+ case I3C_CCC_ENEC:
+ s->can_ibi = true;
+ break;
+ case I3C_CCC_DISEC:
+ s->can_ibi = false;
+ break;
+ case I3C_CCC_ENTDAA:
+ case I3C_CCC_SETAASA:
+ case I3C_CCC_RSTDAA:
+ case I3C_CCCD_SETDASA:
+ case I3C_CCCD_GETPID:
+ case I3C_CCCD_GETBCR:
+ case I3C_CCCD_GETDCR:
+ case I3C_CCCD_GETMWL:
+ case I3C_CCCD_GETMRL:
+ case I3C_CCCD_GETMXDS:
+ case I3C_CCCD_GETCAPS:
+ /* Nothing to do. */
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_ccc);
+ return -1;
+ }
+
+ trace_mock_target_handle_ccc_read(*num_sent, num_to_send);
+ return 0;
+}
+
+static void mock_target_do_ibi(MockTargetState *s)
+{
+ if (!s->can_ibi) {
+ DB_PRINTF("IBIs disabled by controller");
+ return;
+ }
+
+ trace_mock_target_do_ibi(s->i3c.address, true);
+ int nack = i3c_target_send_ibi(&s->i3c, s->i3c.address, /*is_recv=*/true);
+ /* Getting NACKed isn't necessarily an error, just print it out. */
+ if (nack) {
+ DB_PRINTF("NACKed from controller when sending target interrupt.\n");
+ }
+}
+
+static void mock_target_timer_elapsed(void *opaque)
+{
+ MockTargetState *s = MOCK_TARGET(opaque);
+ timer_del(&s->qtimer);
+ mock_target_do_ibi(s);
+}
+
+static void mock_target_reset(I3CTarget *i3c)
+{
+ MockTargetState *s = MOCK_TARGET(i3c);
+ s->can_ibi = false;
+}
+
+static void mock_target_realize(DeviceState *dev, Error **errp)
+{
+ MockTargetState *s = MOCK_TARGET(dev);
+ s->buf = g_new0(uint8_t, s->cfg.buf_size);
+ mock_target_reset(&s->i3c);
+}
+
+static void mock_target_init(Object *obj)
+{
+ MockTargetState *s = MOCK_TARGET(obj);
+ s->can_ibi = false;
+
+ /* For IBIs. */
+ timer_init_ns(&s->qtimer, QEMU_CLOCK_VIRTUAL, mock_target_timer_elapsed, s);
+}
+
+static Property remote_i3c_props[] = {
+ /* The size of the internal buffer. */
+ DEFINE_PROP_UINT32("buf-size", MockTargetState, cfg.buf_size, 0x100),
+ /*
+ * If the mock target receives this number, it will issue an IBI after
+ * 1 second. Disabled if the IBI magic number is 0.
+ */
+ DEFINE_PROP_UINT8("ibi-magic-num", MockTargetState, cfg.ibi_magic, 0x00),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void mock_target_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I3CTargetClass *k = I3C_TARGET_CLASS(klass);
+
+ dc->realize = mock_target_realize;
+ k->event = mock_target_event;
+ k->recv = mock_target_rx;
+ k->send = mock_target_tx;
+ k->handle_ccc_read = mock_target_handle_ccc_read;
+ k->handle_ccc_write = mock_target_handle_ccc_write;
+
+ device_class_set_props(dc, remote_i3c_props);
+}
+
+static const TypeInfo mock_target_info = {
+ .name = TYPE_MOCK_TARGET,
+ .parent = TYPE_I3C_TARGET,
+ .instance_size = sizeof(MockTargetState),
+ .instance_init = mock_target_init,
+ .class_init = mock_target_class_init,
+};
+
+static void mock_target_register_types(void)
+{
+ type_register_static(&mock_target_info);
+}
+
+type_init(mock_target_register_types)
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
index 71e3059f8d..74c5a5dd6e 100644
--- a/hw/i3c/trace-events
+++ b/hw/i3c/trace-events
@@ -34,3 +34,12 @@ legacy_i2c_recv(uint8_t byte) "Legacy I2C recv 0x%" PRIx8
legacy_i2c_send(uint8_t byte) "Legacy I2C send 0x%" PRIx8
legacy_i2c_start_transfer(uint8_t address, bool is_recv) "Legacy I2C START with address 0x%" PRIx8 " is_recv=%d"
legacy_i2c_end_transfer(void) "Legacy I2C STOP"
+
+# mock-target.c
+mock_target_rx(uint8_t byte) "I3C mock target read 0x%" PRIx8
+mock_target_tx(uint8_t byte) "I3C mock target write 0x%" PRIx8
+mock_target_event(uint8_t event) "I3C mock target event 0x%" PRIx8
+mock_target_handle_ccc_read(uint32_t num_read, uint32_t num_to_read) "I3C mock target read %" PRId32 "/%" PRId32 " bytes"
+mock_target_new_ccc(uint8_t ccc) "I3C mock target handle CCC 0x%" PRIx8
+mock_target_handle_ccc_write(uint32_t num_sent, uint32_t num_to_send) "I3C mock target send %" PRId32 "/%" PRId32 " bytes"
+mock_target_do_ibi(uint8_t address, bool is_recv) "I3C mock target IBI with address 0x%" PRIx8 " RnW=%d"
diff --git a/include/hw/i3c/mock-target.h b/include/hw/i3c/mock-target.h
new file mode 100644
index 0000000000..87df0e014b
--- /dev/null
+++ b/include/hw/i3c/mock-target.h
@@ -0,0 +1,60 @@
+#ifndef MOCK_TARGET_H_
+#define MOCK_TARGET_H_
+
+/*
+ * Mock I3C Device
+ *
+ * Copyright (c) 2023 Google LLC
+ *
+ * The mock I3C device can be thought of as a simple EEPROM. It has a buffer,
+ * and the pointer in the buffer is reset to 0 on an I3C STOP.
+ * To write to the buffer, issue a private write and send data.
+ * To read from the buffer, issue a private read.
+ *
+ * The mock target also supports sending target interrupt IBIs.
+ * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number, and
+ * send that number in a private transaction. The mock target will issue an IBI
+ * after 1 second.
+ *
+ * It also supports a handful of CCCs that are typically used when probing I3C
+ * devices.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/timer.h"
+#include "hw/i3c/i3c.h"
+
+#define TYPE_MOCK_TARGET "mock-target"
+OBJECT_DECLARE_SIMPLE_TYPE(MockTargetState, MOCK_TARGET)
+
+struct MockTargetState {
+ I3CTarget i3c;
+
+ /* General device state */
+ bool can_ibi;
+ QEMUTimer qtimer;
+ size_t p_buf;
+ uint8_t *buf;
+
+ /* For Handing CCCs. */
+ bool in_ccc;
+ I3CCCC curr_ccc;
+ uint8_t ccc_byte_offset;
+
+ struct {
+ uint32_t buf_size;
+ uint8_t ibi_magic;
+ } cfg;
+};
+
+#endif
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 14/16] hw/i3c: remote_i3c: Add model
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (12 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 13/16] hw/i3c: Add Mock target Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-04-03 6:13 ` Jeremy Kerr
2023-03-31 1:01 ` [PATCH 15/16] qtest: remote_i3c: Add remote I3C qtest Joe Komlodi
` (2 subsequent siblings)
16 siblings, 1 reply; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
Adds a model to communicate to remote I3C devices over chardev. This
allows QEMU to communicate to I3C targets that exist outside of QEMU.
The remote I3C protocol is as follows:
On an I3C private and CCC TX (controller -> target)
- 1-byte opcode
- 4-byte number of bytes in the packet as a LE uint32
- n-byte payload
On an I3C private and CCC RX (target -> controller)
Controller to target:
- 1-byte opcode
- 4-byte number of bytes to read as a LE uint32
Remote target response:
- 4-byte number of bytes in the packet as a LE uint32
- n-byte payload
IBI (target -> controller, initiated by target)
- 1-byte opcode
- 1-byte IBI address
- 1-byte RnW boolean
- 4-byte length of IBI payload from target as a LE uint32 (can be 0)
- n-byte IBI payload
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
---
hw/i3c/Kconfig | 5 +
hw/i3c/meson.build | 1 +
hw/i3c/remote-i3c.c | 469 ++++++++++++++++++++++++++++++++++++
hw/i3c/trace-events | 7 +
include/hw/i3c/remote-i3c.h | 72 ++++++
5 files changed, 554 insertions(+)
create mode 100644 hw/i3c/remote-i3c.c
create mode 100644 include/hw/i3c/remote-i3c.h
diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig
index f97f4066a9..09b83578f3 100644
--- a/hw/i3c/Kconfig
+++ b/hw/i3c/Kconfig
@@ -10,3 +10,8 @@ config MOCK_TARGET
bool
select I3C
default y if I3C_DEVICES
+
+config REMOTE_I3C
+ bool
+ select I3C
+ default y if I3C_DEVICES
diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build
index 0f6268063e..5bc900de5b 100644
--- a/hw/i3c/meson.build
+++ b/hw/i3c/meson.build
@@ -2,4 +2,5 @@ i3c_ss = ss.source_set()
i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c'))
i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c'))
i3c_ss.add(when: 'CONFIG_MOCK_TARGET', if_true: files('mock-target.c'))
+i3c_ss.add(when: 'CONFIG_REMOTE_I3C', if_true: files('remote-i3c.c'))
softmmu_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss)
diff --git a/hw/i3c/remote-i3c.c b/hw/i3c/remote-i3c.c
new file mode 100644
index 0000000000..20a45e58d9
--- /dev/null
+++ b/hw/i3c/remote-i3c.c
@@ -0,0 +1,469 @@
+/*
+ * Remote I3C Device
+ *
+ * Copyright (c) 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/log.h"
+#include "qemu/fifo8.h"
+#include "chardev/char-fe.h"
+#include "trace.h"
+#include "hw/i3c/i3c.h"
+#include "hw/i3c/remote-i3c.h"
+#include "hw/qdev-properties-system.h"
+
+typedef enum {
+ IBI_RX_STATE_DONE = 0,
+ IBI_RX_STATE_READ_ADDR = 1,
+ IBI_RX_STATE_READ_RNW = 2,
+ IBI_RX_STATE_READ_SIZE = 3,
+ IBI_RX_STATE_READ_DATA = 4,
+} IBIRXState;
+
+typedef struct {
+ uint8_t addr;
+ bool is_recv;
+ uint32_t num_bytes;
+ uint8_t *data;
+} IBIData;
+
+typedef struct {
+ I3CTarget parent_obj;
+ CharBackend chr;
+ /* For ease of debugging. */
+
+ struct {
+ char *name;
+ uint32_t buf_size;
+ } cfg;
+
+ /* Intermediate buffer to store IBI data received over socket. */
+ IBIData ibi_data;
+ Fifo8 tx_fifo;
+ Fifo8 rx_fifo;
+ uint8_t current_cmd;
+ IBIRXState ibi_rx_state;
+ /*
+ * To keep track of where we are in reading in data that's longer than
+ * 1-byte.
+ */
+ uint32_t ibi_bytes_rxed;
+} RemoteI3C;
+
+static uint32_t remote_i3c_recv(I3CTarget *t, uint8_t *data,
+ uint32_t num_to_read)
+{
+ RemoteI3C *i3c = REMOTE_I3C(t);
+ uint8_t type = REMOTE_I3C_RECV;
+ uint32_t num_read;
+
+ qemu_chr_fe_write_all(&i3c->chr, &type, 1);
+ uint32_t num_to_read_le = cpu_to_le32(num_to_read);
+ qemu_chr_fe_write_all(&i3c->chr, (uint8_t *)&num_to_read_le,
+ sizeof(num_to_read_le));
+ /*
+ * The response will first contain the size of the packet, as a LE uint32.
+ */
+ qemu_chr_fe_read_all(&i3c->chr, (uint8_t *)&num_read, sizeof(num_read));
+
+ num_read = le32_to_cpu(num_read);
+ qemu_chr_fe_read_all(&i3c->chr, data, num_read);
+ trace_remote_i3c_recv(i3c->cfg.name, num_read, num_to_read);
+ return num_read;
+}
+
+static inline bool remote_i3c_tx_in_progress(RemoteI3C *i3c)
+{
+ return !fifo8_is_empty(&i3c->tx_fifo);
+}
+
+static int remote_i3c_chr_send_bytes(RemoteI3C *i3c)
+{
+ uint32_t i;
+ uint32_t num_bytes = fifo8_num_used(&i3c->tx_fifo);
+ g_autofree uint8_t *buf = g_new0(uint8_t, num_bytes);
+
+ qemu_chr_fe_write_all(&i3c->chr, &i3c->current_cmd,
+ sizeof(i3c->current_cmd));
+
+ /* The FIFO data is stored in a ring buffer, move it into a linear one. */
+ for (i = 0; i < num_bytes; i++) {
+ buf[i] = fifo8_pop(&i3c->tx_fifo);
+ }
+
+ uint32_t num_bytes_le = cpu_to_le32(num_bytes);
+ qemu_chr_fe_write_all(&i3c->chr, (uint8_t *)&num_bytes_le, 4);
+ qemu_chr_fe_write_all(&i3c->chr, buf, num_bytes);
+ trace_remote_i3c_send(i3c->cfg.name, num_bytes, i3c->current_cmd ==
+ REMOTE_I3C_HANDLE_CCC_WRITE);
+
+ return 0;
+}
+
+static bool remote_i3c_tx_fifo_push(RemoteI3C *i3c, const uint8_t *data,
+ uint32_t num_to_send, uint32_t *num_sent)
+{
+ uint32_t num_to_push = num_to_send;
+ bool ack = true;
+
+ /*
+ * For performance reasons, we buffer data being sent from the controller to
+ * us.
+ * If this FIFO has data in it, we transmit it when we receive an I3C
+ * STOP or START.
+ */
+ if (fifo8_num_free(&i3c->tx_fifo) < num_to_send) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s-%s: TX FIFO buffer full.\n",
+ object_get_canonical_path(OBJECT(i3c)), i3c->cfg.name);
+ num_to_push = fifo8_num_free(&i3c->tx_fifo);
+ ack = false;
+ }
+
+ *num_sent = num_to_push;
+ for (uint32_t i = 0; i < num_to_push; i++) {
+ fifo8_push(&i3c->tx_fifo, data[i]);
+ }
+
+ return ack;
+}
+
+static int remote_i3c_send(I3CTarget *t, const uint8_t *data,
+ uint32_t num_to_send, uint32_t *num_sent)
+{
+ RemoteI3C *i3c = REMOTE_I3C(t);
+ i3c->current_cmd = REMOTE_I3C_SEND;
+ if (!remote_i3c_tx_fifo_push(i3c, data, num_to_send, num_sent)) {
+ return -1;
+ }
+
+ return 0;
+}
+
+static int remote_i3c_handle_ccc_read(I3CTarget *t, uint8_t *data,
+ uint32_t num_to_read, uint32_t *num_read)
+{
+ RemoteI3C *i3c = REMOTE_I3C(t);
+ uint8_t type = REMOTE_I3C_HANDLE_CCC_READ;
+
+ qemu_chr_fe_write_all(&i3c->chr, &type, 1);
+ /*
+ * The response will first contain the size of the packet, as a LE uint32.
+ */
+ qemu_chr_fe_read_all(&i3c->chr, (uint8_t *)num_read, 4);
+ *num_read = le32_to_cpu(*num_read);
+ qemu_chr_fe_read_all(&i3c->chr, data, *num_read);
+ trace_remote_i3c_ccc_read(i3c->cfg.name, *num_read, num_to_read);
+
+ return 0;
+}
+
+static int remote_i3c_handle_ccc_write(I3CTarget *t, const uint8_t *data,
+ uint32_t num_to_send, uint32_t *num_sent)
+{
+ RemoteI3C *i3c = REMOTE_I3C(t);
+ i3c->current_cmd = REMOTE_I3C_HANDLE_CCC_WRITE;
+ if (!remote_i3c_tx_fifo_push(i3c, data, num_to_send, num_sent)) {
+ return -1;
+ }
+
+ return 0;
+}
+
+static int remote_i3c_event(I3CTarget *t, enum I3CEvent event)
+{
+ RemoteI3C *i3c = REMOTE_I3C(t);
+ uint8_t type;
+ trace_remote_i3c_event(i3c->cfg.name, event);
+ switch (event) {
+ case I3C_START_RECV:
+ type = REMOTE_I3C_START_RECV;
+ break;
+ case I3C_START_SEND:
+ type = REMOTE_I3C_START_SEND;
+ break;
+ case I3C_STOP:
+ type = REMOTE_I3C_STOP;
+ break;
+ case I3C_NACK:
+ type = REMOTE_I3C_NACK;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s-%s: Unknown I3C event %d\n",
+ object_get_canonical_path(OBJECT(i3c)), i3c->cfg.name,
+ event);
+ return -1;
+ }
+
+ /*
+ * If we have a transfer buffered, send it out before we tell the remote
+ * target about the next event.
+ */
+ if (remote_i3c_tx_in_progress(i3c)) {
+ remote_i3c_chr_send_bytes(i3c);
+ }
+
+ qemu_chr_fe_write_all(&i3c->chr, &type, 1);
+ return 0;
+}
+
+static void remote_i3c_chr_event(void *opaque, QEMUChrEvent evt)
+{
+ switch (evt) {
+ case CHR_EVENT_OPENED:
+ case CHR_EVENT_CLOSED:
+ case CHR_EVENT_BREAK:
+ case CHR_EVENT_MUX_IN:
+ case CHR_EVENT_MUX_OUT:
+ /*
+ * Ignore events.
+ * Our behavior stays the same regardless of what happens.
+ */
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void remote_i3c_rx_ibi(RemoteI3C *i3c, const uint8_t *buf, int size)
+{
+ uint32_t p_buf = 0;
+ while (p_buf < size) {
+ switch (i3c->ibi_rx_state) {
+ /* This is the start of a new IBI request. */
+ case IBI_RX_STATE_DONE:
+ i3c->ibi_rx_state = IBI_RX_STATE_READ_ADDR;
+ p_buf++;
+ break;
+ case IBI_RX_STATE_READ_ADDR:
+ i3c->ibi_data.addr = buf[p_buf];
+ p_buf++;
+ i3c->ibi_rx_state = IBI_RX_STATE_READ_RNW;
+ break;
+ case IBI_RX_STATE_READ_RNW:
+ i3c->ibi_data.is_recv = buf[p_buf];
+ p_buf++;
+ i3c->ibi_rx_state = IBI_RX_STATE_READ_SIZE;
+ break;
+ case IBI_RX_STATE_READ_SIZE:
+ i3c->ibi_data.num_bytes |= ((uint32_t)buf[p_buf] <<
+ (8 * i3c->ibi_bytes_rxed));
+ i3c->ibi_bytes_rxed++;
+ p_buf++;
+ /*
+ * If we're done reading the num_bytes portion, move on to reading
+ * data.
+ */
+ if (i3c->ibi_bytes_rxed == sizeof(i3c->ibi_data.num_bytes)) {
+ i3c->ibi_data.num_bytes = le32_to_cpu(i3c->ibi_data.num_bytes);
+ i3c->ibi_bytes_rxed = 0;
+ i3c->ibi_rx_state = IBI_RX_STATE_READ_DATA;
+ /* If there's no data to read, we're done. */
+ if (i3c->ibi_data.num_bytes == 0) {
+ /*
+ * Sanity check to see if the remote target is doing
+ * something wonky. This would only happen if it sends
+ * another IBI before the first one has been ACKed/NACKed
+ * by the controller.
+ * We'll try to recover by just exiting early and discarding
+ * the leftover bytes.
+ */
+ if (p_buf < size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s-%s: Remote target "
+ "sent trailing bytes at the end of the "
+ "IBI request.",
+ object_get_canonical_path(OBJECT(i3c)),
+ i3c->cfg.name);
+ return;
+ }
+ i3c->ibi_rx_state = IBI_RX_STATE_DONE;
+ } else {
+ /*
+ * We have IBI bytes to read, allocate memory for it.
+ * Freed when we're done sending the IBI to the controller.
+ */
+ i3c->ibi_data.data = g_new0(uint8_t,
+ i3c->ibi_data.num_bytes);
+ }
+ }
+ break;
+ case IBI_RX_STATE_READ_DATA:
+ i3c->ibi_data.data[i3c->ibi_bytes_rxed] = buf[p_buf];
+ i3c->ibi_bytes_rxed++;
+ p_buf++;
+ if (i3c->ibi_bytes_rxed == i3c->ibi_data.num_bytes) {
+ /*
+ * Sanity check to see if the remote target is doing something
+ * wonky. This would only happen if it sends another IBI before
+ * the first one has been ACKed/NACKed by the controller.
+ * We'll try to recover by just exiting early and discarding the
+ * leftover bytes.
+ */
+ if (p_buf < size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s-%s: Remote target "
+ "sent trailing bytes at the end of the "
+ "IBI request.",
+ object_get_canonical_path(OBJECT(i3c)), i3c->cfg.name);
+ return;
+ }
+ i3c->ibi_rx_state = IBI_RX_STATE_DONE;
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s-%s: Remote target IBI state "
+ "machine reached unknown state 0x%x\n",
+ object_get_canonical_path(OBJECT(i3c)), i3c->cfg.name,
+ i3c->ibi_rx_state);
+ g_assert_not_reached();
+ }
+ }
+}
+
+static void remote_i3c_ibi_rx_state_reset(RemoteI3C *i3c)
+{
+ if (i3c->ibi_data.num_bytes) {
+ free(i3c->ibi_data.data);
+ }
+ i3c->ibi_data.addr = 0;
+ i3c->ibi_data.is_recv = 0;
+ i3c->ibi_data.num_bytes = 0;
+ i3c->ibi_bytes_rxed = 0;
+ i3c->ibi_rx_state = IBI_RX_STATE_DONE;
+}
+
+static void remote_i3c_do_ibi(RemoteI3C *i3c)
+{
+ uint32_t i;
+ uint8_t resp = REMOTE_I3C_IBI_ACK;
+
+ trace_remote_i3c_do_ibi(i3c->cfg.name, i3c->ibi_data.addr,
+ i3c->ibi_data.is_recv);
+ if (i3c_target_send_ibi(&i3c->parent_obj, i3c->ibi_data.addr,
+ i3c->ibi_data.is_recv)) {
+ resp = REMOTE_I3C_IBI_NACK;
+ } else {
+ for (i = 0; i < i3c->ibi_data.num_bytes; i++) {
+ if (i3c_target_send_ibi_bytes(&i3c->parent_obj,
+ i3c->ibi_data.data[i])) {
+ resp = REMOTE_I3C_IBI_DATA_NACK;
+ break;
+ }
+ }
+ }
+
+ if (i3c_target_ibi_finish(&i3c->parent_obj, 0x00)) {
+ resp = REMOTE_I3C_IBI_NACK;
+ }
+ qemu_chr_fe_write_all(&i3c->chr, &resp, sizeof(resp));
+ remote_i3c_ibi_rx_state_reset(i3c);
+}
+
+static int remote_i3c_chr_can_receive(void *opaque)
+{
+ return 1;
+}
+
+static void remote_i3c_chr_receive(void *opaque, const uint8_t *buf, int size)
+{
+ RemoteI3C *i3c = REMOTE_I3C(opaque);
+
+ /*
+ * The only things we expect to receive unprompted are:
+ * - An ACK of a previous transfer
+ * - A NACK of a previous transfer
+ * - An IBI requested by the remote target.
+ * - Bytes for an IBI request.
+ */
+ /* If we're in the middle of handling an IBI request, parse it here. */
+ if (i3c->ibi_rx_state != IBI_RX_STATE_DONE) {
+ remote_i3c_rx_ibi(i3c, buf, size);
+ /* If we finished reading the IBI, do it. */
+ if (i3c->ibi_rx_state == IBI_RX_STATE_DONE) {
+ remote_i3c_do_ibi(i3c);
+ }
+ return;
+ }
+
+ switch (buf[0]) {
+ case REMOTE_I3C_RX_ACK:
+ break;
+ case REMOTE_I3C_RX_NACK:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s-%s: Received NACK from remote "
+ "target\n", object_get_canonical_path(OBJECT(i3c)),
+ i3c->cfg.name);
+ break;
+ case REMOTE_I3C_IBI:
+ remote_i3c_rx_ibi(i3c, buf, size);
+ /* If we finished reading the IBI, do it. */
+ if (i3c->ibi_rx_state == IBI_RX_STATE_DONE) {
+ remote_i3c_do_ibi(i3c);
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s-%s: Unknown response 0x%x\n",
+ object_get_canonical_path(OBJECT(i3c)), i3c->cfg.name,
+ buf[0]);
+ break;
+ }
+}
+
+static void remote_i3c_realize(DeviceState *dev, Error **errp)
+{
+ RemoteI3C *i3c = REMOTE_I3C(dev);
+
+ fifo8_create(&i3c->tx_fifo, i3c->cfg.buf_size);
+ fifo8_create(&i3c->rx_fifo, i3c->cfg.buf_size);
+ i3c->ibi_data.data = g_new0(uint8_t, i3c->cfg.buf_size);
+ remote_i3c_ibi_rx_state_reset(i3c);
+
+ qemu_chr_fe_set_handlers(&i3c->chr, remote_i3c_chr_can_receive,
+ remote_i3c_chr_receive, remote_i3c_chr_event,
+ NULL, OBJECT(i3c), NULL, true);
+}
+
+static Property remote_i3c_props[] = {
+ DEFINE_PROP_CHR("chardev", RemoteI3C, chr),
+ DEFINE_PROP_UINT32("buf-size", RemoteI3C, cfg.buf_size, 0x10000),
+ DEFINE_PROP_STRING("device-name", RemoteI3C, cfg.name),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void remote_i3c_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I3CTargetClass *k = I3C_TARGET_CLASS(klass);
+
+ k->recv = &remote_i3c_recv;
+ k->send = &remote_i3c_send;
+ k->event = &remote_i3c_event;
+ k->handle_ccc_read = &remote_i3c_handle_ccc_read;
+ k->handle_ccc_write = &remote_i3c_handle_ccc_write;
+ device_class_set_props(dc, remote_i3c_props);
+ dc->realize = remote_i3c_realize;
+}
+
+static const TypeInfo remote_i3c_type = {
+ .name = TYPE_REMOTE_I3C,
+ .parent = TYPE_I3C_TARGET,
+ .instance_size = sizeof(RemoteI3C),
+ .class_size = sizeof(I3CTargetClass),
+ .class_init = remote_i3c_class_init,
+};
+
+static void remote_i3c_register(void)
+{
+ type_register_static(&remote_i3c_type);
+}
+
+type_init(remote_i3c_register)
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
index 74c5a5dd6e..ff5efac784 100644
--- a/hw/i3c/trace-events
+++ b/hw/i3c/trace-events
@@ -43,3 +43,10 @@ mock_target_handle_ccc_read(uint32_t num_read, uint32_t num_to_read) "I3C mock t
mock_target_new_ccc(uint8_t ccc) "I3C mock target handle CCC 0x%" PRIx8
mock_target_handle_ccc_write(uint32_t num_sent, uint32_t num_to_send) "I3C mock target send %" PRId32 "/%" PRId32 " bytes"
mock_target_do_ibi(uint8_t address, bool is_recv) "I3C mock target IBI with address 0x%" PRIx8 " RnW=%d"
+
+# remote-i3c.c
+remote_i3c_recv(const char *name, uint32_t num_read, uint32_t num_to_read) "Remote I3C '%s' read %" PRId32 "/%" PRId32 " bytes"
+remote_i3c_send(const char *name, uint32_t num_sent, bool is_ccc) "Remote I3C '%s' send %" PRId32 " bytes, is_ccc=%d"
+remote_i3c_ccc_read(const char *name, uint32_t num_read, uint32_t num_to_read) "Remote I3C '%s' CCC read %" PRId32 "/%" PRId32 " bytes"
+remote_i3c_event(const char *name, uint8_t event) "Remote I3C '%s' event 0x%" PRIx8
+remote_i3c_do_ibi(const char *name, uint8_t addr, bool is_recv) "Remote I3C '%s' IBI with addr 0x%" PRIx8 " RnW=%d"
diff --git a/include/hw/i3c/remote-i3c.h b/include/hw/i3c/remote-i3c.h
new file mode 100644
index 0000000000..822b358098
--- /dev/null
+++ b/include/hw/i3c/remote-i3c.h
@@ -0,0 +1,72 @@
+/*
+ * Remote I3C Device
+ *
+ * Copyright (c) 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+/*
+ * The remote I3C protocol is as follows:
+ * On an I3C private and CCC TX (controller -> target)
+ * - 1-byte opcode
+ * - 4-byte number of bytes in the packet as a LE uint32
+ * - n-byte payload
+ *
+ * On an I3C private and CCC RX (target -> controller)
+ * Controller to target:
+ * - 1-byte opcode
+ * - 4-byte number of bytes to read as a LE uint32
+ * Remote target response:
+ * - 4-byte number of bytes in the packet as a LE uint32
+ * - n-byte payload
+ *
+ * IBI (target -> controller, initiated by target)
+ * - 1-byte opcode
+ * - 1-byte IBI address
+ * - 1-byte RnW boolean
+ * - 4-byte length of IBI payload from target as a LE uint32 (can be 0)
+ * - n-byte IBI payload
+ */
+
+#ifndef REMOTE_I3C_H_
+#define REMOTE_I3C_H_
+
+#define TYPE_REMOTE_I3C "remote-i3c"
+#define REMOTE_I3C(obj) OBJECT_CHECK(RemoteI3C, (obj), TYPE_REMOTE_I3C)
+
+/* 1-byte IBI addr, 1-byte is recv, 4-byte data len. */
+#define REMOTE_I3C_IBI_HDR_LEN 6
+
+/* Stored in a uint8_t */
+typedef enum {
+ /* Sent from us to remote target. */
+ REMOTE_I3C_START_RECV = 1,
+ REMOTE_I3C_START_SEND = 2,
+ REMOTE_I3C_STOP = 3,
+ REMOTE_I3C_NACK = 4,
+ REMOTE_I3C_RECV = 5,
+ REMOTE_I3C_SEND = 6,
+ REMOTE_I3C_HANDLE_CCC_WRITE = 7,
+ REMOTE_I3C_HANDLE_CCC_READ = 8,
+ REMOTE_I3C_IBI = 9,
+ /* Sent from remote target to us. */
+ REMOTE_I3C_IBI_ACK = 0xc0,
+ REMOTE_I3C_IBI_NACK = 0xc1,
+ REMOTE_I3C_IBI_DATA_NACK = 0xc2,
+} RemoteI3CCommand;
+
+typedef enum {
+ REMOTE_I3C_RX_ACK = 0,
+ REMOTE_I3C_RX_NACK = 1,
+} RemoteI3CRXEvent;
+
+#endif
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 14/16] hw/i3c: remote_i3c: Add model
2023-03-31 1:01 ` [PATCH 14/16] hw/i3c: remote_i3c: Add model Joe Komlodi
@ 2023-04-03 6:13 ` Jeremy Kerr
2023-04-05 2:04 ` Joe Komlodi
0 siblings, 1 reply; 30+ messages in thread
From: Jeremy Kerr @ 2023-04-03 6:13 UTC (permalink / raw)
To: Joe Komlodi, qemu-devel; +Cc: venture, peter.maydell
Hi Joe,
> Adds a model to communicate to remote I3C devices over chardev. This
> allows QEMU to communicate to I3C targets that exist outside of QEMU.
Nice!
I've been wanting something similar for a while, both for i2c and i3c
busses, to the point of having a similar concept partly implemented.
A couple of design decisions though:
1) Is this something that qemu upstream would accept? Do we need a
formal description of the guest-to-host interface somewhere? Or is there
a more standard way of exposing busses like this?
2) My approach was at the bus level rather than the device level: the
protocol is bidirectional to allow the model to either participate as a
i3c controller or a target. There's quite a bit of mis-fit when applying
that to the qemu device structure though, so your approach is a lot
cleaner.
I'll have a go at adapting my client to your protocol, and see how the
device interface goes.
Assuming we do adopt your approach though, I think the protocol
description needs some work. There seems to be other messages not listed
in your protocol comments, and the direction of some seems to be
reversed. I'm happy to contribute to that documentation if you like.
Cheers,
Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 14/16] hw/i3c: remote_i3c: Add model
2023-04-03 6:13 ` Jeremy Kerr
@ 2023-04-05 2:04 ` Joe Komlodi
2023-04-05 2:44 ` Jeremy Kerr
0 siblings, 1 reply; 30+ messages in thread
From: Joe Komlodi @ 2023-04-05 2:04 UTC (permalink / raw)
To: Jeremy Kerr; +Cc: qemu-devel, venture, peter.maydell
Hi Jeremy,
On Sun, Apr 2, 2023 at 11:14 PM Jeremy Kerr <jk@codeconstruct.com.au> wrote:
>
> Hi Joe,
>
> > Adds a model to communicate to remote I3C devices over chardev. This
> > allows QEMU to communicate to I3C targets that exist outside of QEMU.
>
> Nice!
>
> I've been wanting something similar for a while, both for i2c and i3c
> busses, to the point of having a similar concept partly implemented.
>
> A couple of design decisions though:
>
> 1) Is this something that qemu upstream would accept? Do we need a
> formal description of the guest-to-host interface somewhere? Or is there
> a more standard way of exposing busses like this?
>
Not sure! I'm open to ideas.
I think the most controversial portion of the remote target like this
might be doing socket transfers in an MMIO context.
i.e. driver does a write to I3C controller -> triggers a transaction
to remote target -> remote target sends/reads data over socket.
Because of that, we might need to add a way to do these transactions
asynchronously.
> 2) My approach was at the bus level rather than the device level: the
> protocol is bidirectional to allow the model to either participate as a
> i3c controller or a target. There's quite a bit of mis-fit when applying
> that to the qemu device structure though, so your approach is a lot
> cleaner.
>
> I'll have a go at adapting my client to your protocol, and see how the
> device interface goes.
>
> Assuming we do adopt your approach though, I think the protocol
> description needs some work. There seems to be other messages not listed
> in your protocol comments, and the direction of some seems to be
> reversed. I'm happy to contribute to that documentation if you like.
Oops. I'll reread and revise in v2. If you have anything else you want
to add too, let me know and I'll add them as well.
Thanks,
Joe
>
> Cheers,
>
>
> Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 14/16] hw/i3c: remote_i3c: Add model
2023-04-05 2:04 ` Joe Komlodi
@ 2023-04-05 2:44 ` Jeremy Kerr
0 siblings, 0 replies; 30+ messages in thread
From: Jeremy Kerr @ 2023-04-05 2:44 UTC (permalink / raw)
To: Joe Komlodi; +Cc: qemu-devel, venture, peter.maydell
Hi Joe,
> > 1) Is this something that qemu upstream would accept? Do we need a
> > formal description of the guest-to-host interface somewhere? Or is there
> > a more standard way of exposing busses like this?
> >
> Not sure! I'm open to ideas.
> I think the most controversial portion of the remote target like this
> might be doing socket transfers in an MMIO context.
> i.e. driver does a write to I3C controller -> triggers a transaction
> to remote target -> remote target sends/reads data over socket.
>
> Because of that, we might need to add a way to do these transactions
> asynchronously.
OK, that plus the general concept of having a socket interface to the i3c
bus might need a review from someone above my qemu pay-grade.
but, on the assumption that those are acceptable in general:
> > Assuming we do adopt your approach though, I think the protocol
> > description needs some work. There seems to be other messages not listed
> > in your protocol comments, and the direction of some seems to be
> > reversed. I'm happy to contribute to that documentation if you like.
>
> Oops. I'll reread and revise in v2. If you have anything else you want
> to add too, let me know and I'll add them as well.
So I implemented a little daemon for the other side of the socket
interface. I have a few thoughts on the protocol structure:
* can we change the target -> controller read response messages (data +
len) into a normal message type (ie, assign an opcode and use that in
the header)? We may want to use separate opcodes for each response
type.
* I would suggest expanding the start behaviour a little: the message
could contain the target address, and the target responds with an
ACK/NACK event. The model would need to block on the response in
order to return the correct ACK/NACK value (and pass to the
hardware), but this means we can either implement the protocol at the
bus level, or at the individual-device level.
(with the current standalone NACK event, I don't see how a model
could reliably handle that)
* I'm not clear on why the RemoteI3CRXEvents are defined separately.
Can these just be normal messages with an opcode (and no payload)?
I've yet to implement IBIs though, that's next on my list. Happy to chat
separately if this gets off-topic for the qemu general discussion.
Overall though, this is great work! Thanks for the contributions.
Cheers,
Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 15/16] qtest: remote_i3c: Add remote I3C qtest
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (13 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 14/16] hw/i3c: remote_i3c: Add model Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-03-31 1:01 ` [PATCH 16/16] hw/i3c: Add hotplug support Joe Komlodi
2023-04-01 17:28 ` [PATCH 00/16] i3c: aspeed: Add I3C support Ben Dooks
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
This adds a remote I3C qtest using the Aspeed I3C controller and an
AST2600 board.
The qtest uses a basic Aspeed I3C driver to test:
- data transmission from controller to target
- data reception from target to controller
- target sending an IBI (with data bytes) to controller
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/arm/Kconfig | 1 +
tests/qtest/meson.build | 1 +
tests/qtest/remote-i3c-test.c | 610 ++++++++++++++++++++++++++++++++++
3 files changed, 612 insertions(+)
create mode 100644 tests/qtest/remote-i3c-test.c
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a6ca5a9c55..fa67769d1d 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -455,6 +455,7 @@ config ASPEED_SOC
select FTGMAC100
select I2C
select I3C
+ select I3C_DEVICES
select DPS310
select PCA9552
select SERIAL
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 85ea4e8d99..480e11558e 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -190,6 +190,7 @@ qtests_npcm7xx = \
qtests_aspeed = \
['aspeed_hace-test',
'aspeed_smc-test',
+ 'remote-i3c-test',
'aspeed_gpio-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
diff --git a/tests/qtest/remote-i3c-test.c b/tests/qtest/remote-i3c-test.c
new file mode 100644
index 0000000000..49c993ea64
--- /dev/null
+++ b/tests/qtest/remote-i3c-test.c
@@ -0,0 +1,610 @@
+/*
+ * QTest testcase for the remote I3C device, using the AST2600 I3C controller.
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+#include "hw/registerfields.h"
+#include "hw/i3c/i3c.h"
+#include "hw/i3c/remote-i3c.h"
+#include "hw/i3c/aspeed_i3c.h"
+
+/* Starting address of the AST2600 I3C block. */
+#define ASPEED_I3C_BASE 0x1e7a0000
+/* Offset to the first controller in the block. */
+#define ASPEED_I3C_CONTROLLER_OFFSET 0x2000
+#define I3C(x) (ASPEED_I3C_BASE + ASPEED_I3C_CONTROLLER_OFFSET + ((x) * 0x1000))
+#define TARGET_ADDR 0x10
+
+/* I3C Device Registers */
+REG32(DEVICE_CTRL, 0x00)
+ FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1)
+ FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1)
+ FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1)
+ FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2)
+ FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1)
+ FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1)
+ FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1)
+ FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1)
+ FIELD(DEVICE_CTRL, I3C_EN, 31, 1)
+REG32(COMMAND_QUEUE_PORT, 0x0c)
+ FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3)
+ /* Transfer command structure */
+ FIELD(COMMAND_QUEUE_PORT, TID, 3, 4)
+ FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8)
+ FIELD(COMMAND_QUEUE_PORT, CP, 15, 1)
+ FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5)
+ FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3)
+ FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1)
+ FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1)
+ FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1)
+ FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1)
+ FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1)
+ /* Transfer argument data structure */
+ FIELD(COMMAND_QUEUE_PORT, DB, 8, 8)
+ FIELD(COMMAND_QUEUE_PORT, DL, 16, 16)
+ /* Short data argument data structure */
+ FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3)
+ FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8)
+ FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8)
+ FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8)
+ /* Address assignment command structure */
+ /*
+ * bits 3..21 and 26..31 are the same as the transfer command structure, or
+ * marked as reserved.
+ */
+ FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3)
+REG32(RESPONSE_QUEUE_PORT, 0x10)
+ FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16)
+ FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8)
+ FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4)
+ FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4)
+REG32(RX_TX_DATA_PORT, 0x14)
+REG32(IBI_QUEUE_STATUS, 0x18)
+ FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8)
+ FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8)
+ FIELD(IBI_QUEUE_STATUS, IBI_RX_STATUS, 28, 4)
+REG32(IBI_QUEUE_DATA, 0x18)
+REG32(QUEUE_STATUS_LEVEL, 0x4c)
+ FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8)
+ FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8)
+ FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8)
+ FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5)
+REG32(DATA_BUFFER_STATUS_LEVEL, 0x50)
+ FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8)
+ FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8)
+/* Dev addr table fields */
+REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
+ FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8)
+
+typedef union AspeedI3CResponse {
+ uint32_t word;
+ uint16_t data_len;
+ uint8_t ccc_type;
+ uint8_t tid:4;
+ uint8_t err:4;
+} AspeedI3CResponse;
+
+static int sock;
+static int fd;
+
+static in_port_t open_socket(void)
+{
+ struct sockaddr_in myaddr;
+ struct timeval timeout = { .tv_sec = 1, };
+ socklen_t addrlen;
+
+ myaddr.sin_family = AF_INET;
+ myaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
+ myaddr.sin_port = 0;
+ sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
+ g_assert(sock != -1);
+ g_assert(bind(sock, (struct sockaddr *) &myaddr, sizeof(myaddr)) != -1);
+ setsockopt(sock, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
+
+ addrlen = sizeof(myaddr);
+ g_assert(getsockname(sock, (struct sockaddr *) &myaddr , &addrlen) != -1);
+ g_assert(listen(sock, 1) != -1);
+ return ntohs(myaddr.sin_port);
+}
+
+static void setup_fd(void)
+{
+ fd_set readfds;
+
+ FD_ZERO(&readfds);
+ FD_SET(sock, &readfds);
+ g_assert(select(sock + 1, &readfds, NULL, NULL, NULL) == 1);
+
+ fd = accept(sock, NULL, 0);
+}
+
+static AspeedI3CTransferCmd aspeed_i3c_create_xfer_cmd(uint8_t cmd,
+ uint8_t dev_index,
+ bool rnw,
+ bool dbp)
+{
+ return ((AspeedI3CTransferCmd) {
+ .cmd_attr = ASPEED_I3C_CMD_ATTR_TRANSFER_CMD,
+ .tid = 0x01,
+ .cmd = cmd,
+ .cp = (cmd != 0) ? 1 : 0,
+ .dev_index = dev_index,
+ .speed = 0, /* SDR */
+ .dbp = dbp,
+ .roc = 1,
+ .sdap = (cmd == 0x02) ? 1 : 0, /* Short data arg present. */
+ .rnw = rnw,
+ .toc = 1,
+ .pec = 0
+ });
+}
+
+static AspeedI3CTransferArg aspeed_i3c_create_xfer_arg(uint8_t db,
+ uint16_t data_len)
+{
+ return ((AspeedI3CTransferArg) {
+ .cmd_attr = ASPEED_I3C_CMD_ATTR_TRANSFER_ARG,
+ .db = db,
+ .data_len = data_len,
+ });
+}
+
+static void aspeed_i3c_enable(uint32_t base)
+{
+ uint32_t val = readl(base + A_DEVICE_CTRL);
+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 1);
+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_EN, 1);
+ writel(base + A_DEVICE_CTRL, val);
+ /*
+ * Sanity check the enable write. I3C_RESUME is auto-cleared so don't
+ * check it.
+ */
+ g_assert(readl(base + A_DEVICE_CTRL) & R_DEVICE_CTRL_I3C_EN_MASK);
+}
+
+static AspeedI3CResponse aspeed_i3c_read_resp(uint32_t base)
+{
+ AspeedI3CResponse resp;
+ uint32_t queue_status = readl(base + A_QUEUE_STATUS_LEVEL);
+ /* No response to read. */
+ if (FIELD_EX32(queue_status, QUEUE_STATUS_LEVEL, RESP_BUF_BLR) == 0) {
+ resp.word = 0;
+ } else {
+ resp.word = readl(base + A_DEVICE_CTRL);
+ }
+ return resp;
+}
+
+static void aspeed_i3c_send(uint32_t base, uint8_t dev_index,
+ const uint32_t *data, uint16_t len)
+{
+ AspeedI3CCmdQueueData cmd;
+ AspeedI3CCmdQueueData arg;
+ uint16_t words_txed = 0;
+
+ /* Start doing the transfer. */
+ while (words_txed < len) {
+ /* Push data to the TX queue. */
+ uint32_t tx_num_empty = FIELD_EX32(readl(base +
+ A_DATA_BUFFER_STATUS_LEVEL),
+ DATA_BUFFER_STATUS_LEVEL,
+ TX_BUF_EMPTY_LOC);
+ for (uint16_t i = 0; i < tx_num_empty; i++) {
+ writel(base + A_RX_TX_DATA_PORT, data[words_txed]);
+ words_txed++;
+ /* We have no more to transfer, bail early. */
+ if (words_txed >= len) {
+ break;
+ }
+ }
+
+ /* Now that the data is in the queue, we can start our transfer. */
+ /*
+ * CMD is ignored due to this not being a CCC, and there is no defining
+ * byte, also because this isn't a CCC.
+ */
+ cmd.transfer_cmd = aspeed_i3c_create_xfer_cmd(0, dev_index, false,
+ false);
+ arg.transfer_arg = aspeed_i3c_create_xfer_arg(0, len * sizeof(*data));
+ /* Order to push is arg then command. */
+ writel(base + A_COMMAND_QUEUE_PORT, arg.word);
+ writel(base + A_COMMAND_QUEUE_PORT, cmd.word);
+ }
+}
+
+static void aspeed_i3c_send_ccc(uint32_t base, uint8_t ccc_cmd)
+{
+ AspeedI3CCmdQueueData cmd;
+ AspeedI3CCmdQueueData arg;
+
+ cmd.transfer_cmd = aspeed_i3c_create_xfer_cmd(ccc_cmd, 0, false,
+ false);
+ arg.transfer_arg = aspeed_i3c_create_xfer_arg(0, 0);
+ /* Order to push is arg then command. */
+ writel(base + A_COMMAND_QUEUE_PORT, arg.word);
+ writel(base + A_COMMAND_QUEUE_PORT, cmd.word);
+}
+
+static void aspeed_i3c_recv(uint32_t base, uint8_t dev_index, uint8_t *data,
+ uint16_t len)
+{
+ AspeedI3CCmdQueueData cmd;
+ AspeedI3CCmdQueueData arg;
+ uint16_t bytes_rxed = 0;
+ uint32_t *p32_data = (uint32_t *)data;
+
+ /* Start doing the transfer. */
+ while (bytes_rxed < len) {
+ /* Send the RX request. */
+ /*
+ * CMD is ignored due to this not being a CCC, and there is no defining
+ * byte, also because this isn't a CCC.
+ */
+ cmd.transfer_cmd = aspeed_i3c_create_xfer_cmd(0, dev_index, true,
+ false);
+ uint16_t num_to_rx = (len - bytes_rxed) > ASPEED_I3C_RX_QUEUE_CAPACITY ?
+ ASPEED_I3C_RX_QUEUE_CAPACITY : (len - bytes_rxed);
+ arg.transfer_arg = aspeed_i3c_create_xfer_arg(0, num_to_rx);
+ /* Order to push is arg then command. */
+ writel(base + A_COMMAND_QUEUE_PORT, arg.word);
+ writel(base + A_COMMAND_QUEUE_PORT, cmd.word);
+
+ /* Read the data from the data RX queue. */
+ uint32_t rx_word_num =
+ FIELD_EX32(readl(base + A_DATA_BUFFER_STATUS_LEVEL),
+ DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR);
+ for (uint16_t i = 0; i < rx_word_num; i++) {
+ *p32_data = readl(base + A_RX_TX_DATA_PORT);
+ p32_data++;
+ bytes_rxed += 4;
+ }
+ }
+}
+
+static void assert_good_resp(uint32_t base)
+{
+ /* We expect a good response from this. */
+ AspeedI3CResponse resp = aspeed_i3c_read_resp(base);
+ g_assert(resp.err == ASPEED_I3C_RESP_QUEUE_ERR_NONE);
+}
+
+static void read_data(uint8_t *data, size_t len)
+{
+ ssize_t ret;
+ size_t len_read = 0;
+
+ while (len_read < len) {
+ ret = read(fd, &data[len_read], len);
+ g_assert(ret != -1);
+ len_read += ret;
+ }
+}
+
+static void remote_i3c_read_and_verify(const uint8_t *expected_data, size_t len)
+{
+ g_autofree uint8_t *data_read = g_new0(uint8_t, len);
+
+ read_data(data_read, len);
+ g_assert(memcmp(data_read, expected_data, len) == 0);
+}
+
+static void add_targets_to_bus(uint32_t base)
+{
+ /* Arbitrary large enough size. */
+ uint8_t remote_target_expected_data[8];
+
+ /* Send SATAASA to the remote target. */
+ aspeed_i3c_send_ccc(base, I3C_CCC_SETAASA);
+ /*
+ * Verify everything is good.
+ * The remote target should receive:
+ * - an I3C_START event
+ * - the size of the CCC packet as a LE uint32
+ * - the CCC
+ * - then an I3C_STOP event.
+ * The controller should have a good response in the queue.
+ */
+ assert_good_resp(base);
+ remote_target_expected_data[0] = REMOTE_I3C_START_SEND;
+ remote_target_expected_data[1] = REMOTE_I3C_HANDLE_CCC_WRITE;
+ uint32_t *p32 = (uint32_t *)&remote_target_expected_data[2];
+ *p32 = htole32(1);
+ remote_target_expected_data[6] = I3C_CCC_SETAASA;
+ remote_target_expected_data[7] = REMOTE_I3C_STOP;
+ remote_i3c_read_and_verify(remote_target_expected_data, 8);
+
+ /*
+ * Populate the device table. On a real system we would either:
+ * - populate the table and send ENTDAA, then probe the addresses to see who
+ * exists.
+ * - SETAASA and then go through a list addresses to see who exists, probe
+ * them, and add them to the table.
+ * We're doing the SETAASA way, minus the probing portion, so just add the
+ * known address to the table.
+ */
+ uint32_t val = 0;
+ val = FIELD_DP32(val, DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR,
+ TARGET_ADDR);
+ writel(base + A_DEVICE_ADDR_TABLE_LOC1, val);
+}
+
+static void send_and_verify(uint32_t i3c_base, const uint32_t *data, size_t len)
+{
+ /*
+ * Add padding to the data_read packet, since the remote target will receive
+ * extra bytes that include the I3C START and STOP events, along with the
+ * length of the packet, and the data packet itself.
+ */
+ uint32_t data_size = len * sizeof(*data);
+ size_t expected_data_len = data_size + 7;
+ g_autofree uint8_t *remote_target_expected_data = g_new0(uint8_t,
+ expected_data_len);
+ remote_target_expected_data[0] = REMOTE_I3C_START_SEND;
+ remote_target_expected_data[1] = REMOTE_I3C_SEND;
+ uint32_t *p32 = (uint32_t *)&remote_target_expected_data[2];
+ *p32 = htole32(data_size);
+ memcpy(&remote_target_expected_data[6], data, data_size);
+ remote_target_expected_data[data_size + 6] = REMOTE_I3C_STOP;
+
+ aspeed_i3c_send(i3c_base, 0, data, len);
+ assert_good_resp(i3c_base);
+ remote_i3c_read_and_verify(remote_target_expected_data, expected_data_len);
+}
+
+/* Remote target RX, e.g. controller -> target. */
+static void test_remote_i3c_rx(gconstpointer test_data)
+{
+ uint32_t controller_num = *(uint32_t *)test_data;
+ uint32_t i3c_base = I3C(controller_num);
+ /*
+ * The Aspeed controller expects data in 32-bit words, so make this 32-bits.
+ */
+ const uint32_t data[] = {7, 6, 5, 4, 3, 2, 1, 0};
+ /* Enable the controller. */
+ aspeed_i3c_enable(i3c_base);
+ /*
+ * Tell the target to use its static address as its dynamic address, and
+ * populate the device table.
+ */
+ add_targets_to_bus(i3c_base);
+ /* Now we can test sending data to the target. */
+ send_and_verify(i3c_base, data, ARRAY_SIZE(data));
+}
+
+static void read_and_verify(uint32_t i3c_base, const uint8_t *data, size_t len)
+{
+ g_autofree uint8_t *data_received = g_new0(uint8_t, len);
+
+ /* Send the I3C recv request. */
+ aspeed_i3c_recv(i3c_base, 0, data_received, len);
+ /*
+ * Verify everything is okay. Anything on the remote I3C protocol level is
+ * handled by the remote target thread. We just need to check that we
+ * received what we expected.
+ */
+ assert_good_resp(i3c_base);
+ g_assert(memcmp(data_received, data, len) == 0);
+}
+
+static void *remote_target_thread(void *arg)
+{
+ uint8_t byte;
+ uint32_t bytes_to_send;
+ uint32_t bytes_to_send_le;
+ const uint8_t *data = (const uint8_t *)arg;
+
+ /* Loop forever reading and parsing incoming data. */
+ while (1) {
+ /*
+ * We can error out during program teardown due to the socket closing,
+ * so don't assert.
+ * If this has a proper error during test, the main thread will error
+ * due to the target thread (this one) not sending anything.
+ */
+ if (read(fd, &byte, 1) != 1) {
+ break;
+ }
+
+ switch (byte) {
+ case REMOTE_I3C_START_RECV:
+ case REMOTE_I3C_STOP:
+ /* Don't care, do nothing. */
+ break;
+ case REMOTE_I3C_RECV:
+ /* Read in the number of bytes the controller wants. */
+ g_assert(read(fd, &bytes_to_send_le, sizeof(bytes_to_send_le)) ==
+ sizeof(bytes_to_send_le));
+ bytes_to_send = le32toh(bytes_to_send_le);
+
+ /*
+ * Send the data. We first send the number of bytes we're sending as
+ * a uint32 LE word (which is the same as the number of bytes the
+ * controller is expecting), followed by the data.
+ */
+ g_assert(write(fd, (uint8_t *)&bytes_to_send_le,
+ sizeof(bytes_to_send_le)) ==
+ sizeof(bytes_to_send_le));
+ g_assert(write(fd, data, bytes_to_send) == bytes_to_send);
+ break;
+ default:
+ g_printerr("Remote target received unknown byte 0x%.2x\n", byte);
+ g_assert_not_reached();
+ }
+ }
+
+ return NULL;
+}
+
+/* Remote target TX, e.g. target -> controller. */
+static void test_remote_i3c_tx(gconstpointer test_data)
+{
+ uint32_t controller_num = *(uint32_t *)test_data;
+ uint32_t i3c_base = I3C(controller_num);
+ /* Non-const since the thread prototype needs a non-const pointer. */
+ uint8_t data[] = {7, 6, 5, 4, 3, 2, 1, 0};
+ GThread *target_thread;
+ /* Enable the controller. */
+ aspeed_i3c_enable(i3c_base);
+ /*
+ * Tell the target to use its static address as its dynamic address, and
+ * populate the device table.
+ */
+ add_targets_to_bus(i3c_base);
+
+ /*
+ * Now we can test receiving data from the target.
+ * The target will need to respond while the controller is doing the I3C
+ * receive (meaning we will be blocked on the remote target sending data to
+ * us), so we need to make a separate thread for the remote target to send
+ * data to the controller.
+ */
+ target_thread = g_thread_new("remote-target", remote_target_thread, data);
+ read_and_verify(i3c_base, data, ARRAY_SIZE(data));
+ g_thread_join(target_thread);
+}
+
+static void remote_i3c_ibi(const uint32_t *data, uint32_t len)
+{
+ /* Convert len to bytes to make math cleaner. */
+ len *= sizeof(uint32_t);
+ /*
+ * IBI format is:
+ * - 1-byte REMOTE_I3C_IBI request.
+ * - 1-byte address of target sending the IBI.
+ * - 1-byte RnW bit.
+ * - 4-byte size of IBI payload.
+ * - n-byte IBI payload.
+ */
+ size_t ibi_req_size = 7 + len;
+ g_autofree uint8_t *ibi_req = g_new0(uint8_t, ibi_req_size);
+ uint32_t len_le;
+ uint8_t ibi_resp;
+
+ ibi_req[0] = REMOTE_I3C_IBI;
+ ibi_req[1] = TARGET_ADDR;
+ ibi_req[2] = 0; /* RnW = 0 to make this a target interrupt request. */
+ len_le = htole32(len);
+ memcpy(&ibi_req[3], &len_le, sizeof(len_le));
+ memcpy(&ibi_req[7], data, len);
+
+ /* Send the request and read back the ACK. */
+ g_assert(write(fd, ibi_req, ibi_req_size) == ibi_req_size);
+ g_assert(read(fd, &ibi_resp, sizeof(ibi_resp)) == sizeof(ibi_resp));
+ g_assert(ibi_resp == REMOTE_I3C_IBI_ACK);
+}
+
+static void aspeed_i3c_read_ibi_and_verify(uint32_t i3c_base,
+ const uint32_t *data, size_t len)
+{
+ g_autofree uint32_t *ibi_data = g_new0(uint32_t, len * sizeof(uint32_t));
+
+ /* Make sure there's actually something to read in the IBI queue. */
+ uint8_t ibi_buf_lvl = FIELD_EX32(readl(i3c_base + A_QUEUE_STATUS_LEVEL),
+ QUEUE_STATUS_LEVEL, IBI_BUF_BLR);
+ /*
+ * ibi_buf_level should have 1-byte for IBI status, plus data size in words.
+ */
+ g_assert(ibi_buf_lvl == 1 + len);
+ uint32_t ibi_status = readl(i3c_base + A_IBI_QUEUE_STATUS);
+ /* IBI_ID is target address << 1 | RnW bit (which is 0) */
+ g_assert(FIELD_EX32(ibi_status, IBI_QUEUE_STATUS, IBI_ID) ==
+ (TARGET_ADDR << 1));
+ /* IBI data length in the register is stored in bytes. */
+ uint32_t ibi_data_len = FIELD_EX32(ibi_status, IBI_QUEUE_STATUS,
+ IBI_DATA_LEN);
+ g_assert(ibi_data_len == len * sizeof(uint32_t));
+
+ /*
+ * Read in the IBI bytes, if they aren't word-aligned, read in an extra
+ * word.
+ */
+ for (size_t i = 0; i < (ibi_data_len / 4) +
+ (ibi_data_len & 0x03) ? 1 : 0; i++) {
+ ibi_data[i] = readl(i3c_base + A_IBI_QUEUE_DATA);
+ }
+ /* Make sure the data matches. */
+ g_assert(memcmp(ibi_data, data, len) == 0);
+}
+
+static void ibi_and_verify(uint32_t i3c_base, const uint32_t *data, size_t len)
+{
+ /* Send the IBI request. */
+ remote_i3c_ibi(data, len);
+ /* Read it and verify it matches what we expect. */
+ aspeed_i3c_read_ibi_and_verify(i3c_base, data, len);
+}
+
+/* Remote target IBI. */
+static void test_remote_i3c_ibi(gconstpointer test_data)
+{
+ uint32_t controller_num = *(uint32_t *)test_data;
+ uint32_t i3c_base = I3C(controller_num);
+ uint32_t data = 0xaa55cc33;
+ /* Enable the controller. */
+ aspeed_i3c_enable(i3c_base);
+ /*
+ * Tell the target to use its static address as its dynamic address, and
+ * populate the device table.
+ */
+ add_targets_to_bus(i3c_base);
+
+ /*
+ * To test IBIing, we will:
+ * - Have the target IBI the controller by writing to the socket.
+ * - The controller ACKs and enqueues the IBI request.
+ * - The ACK is sent over socket, we verify it's there.
+ * - We read the request from the controller IBI queue.
+ */
+ ibi_and_verify(i3c_base, &data, 1);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+ int port;
+ /* Global register base address + offset of first controller. */
+ uint32_t i3c_controller_num = 0;
+ g_test_init(&argc, &argv, NULL);
+ port = open_socket();
+
+ global_qtest = qtest_initf("-machine ast2600-evb "
+ "-chardev socket,id=remote-i3c-chr,port=%d,host=localhost "
+ "-device %s,"
+ "chardev=remote-i3c-chr,"
+ "device-name=remote-target,"
+ "bus=aspeed.i3c.device.0,"
+ "pid=0xfeedf00dd00d,"
+ "dcr=0xaa,"
+ "bcr=0x55,"
+ "static-address=%d",
+ port, TYPE_REMOTE_I3C, TARGET_ADDR);
+ setup_fd();
+
+ /* Remote target RXing, i.e. controller -> target. */
+ qtest_add_data_func("remote-i3c-rx", (void *)&i3c_controller_num,
+ test_remote_i3c_rx);
+ /* Remote target TXing, i.e. controller -> target. */
+ qtest_add_data_func("remote-i3c-tx", (void *)&i3c_controller_num,
+ test_remote_i3c_tx);
+ /* Remote target IBIing. */
+ qtest_add_data_func("remote-i3c-ibi", (void *)&i3c_controller_num,
+ test_remote_i3c_ibi);
+
+ ret = g_test_run();
+ qtest_end();
+
+ return ret;
+}
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 16/16] hw/i3c: Add hotplug support
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (14 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 15/16] qtest: remote_i3c: Add remote I3C qtest Joe Komlodi
@ 2023-03-31 1:01 ` Joe Komlodi
2023-04-01 17:28 ` [PATCH 00/16] i3c: aspeed: Add I3C support Ben Dooks
16 siblings, 0 replies; 30+ messages in thread
From: Joe Komlodi @ 2023-03-31 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: venture, komlodi, peter.maydell
This adds support for hotplugging in I3C.
Conceptually this can be thought of as an I3C target being physically
socketed onto a board.
It is then the target's responsibility to go through the hot-join and
DAA process so it can participate on the bus.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
---
hw/i3c/core.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/hw/i3c/core.c b/hw/i3c/core.c
index 758dd7141f..c6ef16bbba 100644
--- a/hw/i3c/core.c
+++ b/hw/i3c/core.c
@@ -19,6 +19,7 @@
#include "qapi/error.h"
#include "trace.h"
#include "hw/i3c/i3c.h"
+#include "hw/hotplug.h"
#include "hw/qdev-properties.h"
static Property i3c_props[] = {
@@ -29,11 +30,27 @@ static Property i3c_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static void i3c_realize(BusState *bus, Error **errp)
+{
+ qbus_set_bus_hotplug_handler(bus);
+}
+
+static void i3c_class_init(ObjectClass *klass, void *data)
+{
+ BusClass *k = BUS_CLASS(klass);
+ k->realize = i3c_realize;
+}
+
static const TypeInfo i3c_bus_info = {
.name = TYPE_I3C_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(I3CBus),
.class_size = sizeof(I3CBusClass),
+ .class_init = i3c_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_HOTPLUG_HANDLER },
+ { }
+ }
};
I3CBus *i3c_init_bus(DeviceState *parent, const char *name)
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 00/16] i3c: aspeed: Add I3C support
2023-03-31 1:01 [PATCH 00/16] i3c: aspeed: Add I3C support Joe Komlodi
` (15 preceding siblings ...)
2023-03-31 1:01 ` [PATCH 16/16] hw/i3c: Add hotplug support Joe Komlodi
@ 2023-04-01 17:28 ` Ben Dooks
2023-04-02 7:33 ` Cédric Le Goater
16 siblings, 1 reply; 30+ messages in thread
From: Ben Dooks @ 2023-04-01 17:28 UTC (permalink / raw)
To: Joe Komlodi; +Cc: qemu-devel, venture, peter.maydell
On Fri, Mar 31, 2023 at 01:01:15AM +0000, Joe Komlodi wrote:
> Hi all,
>
> This series adds I3C bus support to QEMU and adds more functionality to the
> Aspeed I3C controller.
>
> This implementation is a basic implementation that introduces IBIs
> (including hot-join), CCCs, and SDR data transfer. As-is, it doesnt support
> multi-controller buses or HDR transfers.
>
> First we add the I3C bus and controller model. With that added we
> gradually extend the functionality of the Aspeed I3C controller so it
> can do transfers.
>
> With that added, we add 2 targets. The first target is a mock I3C
> target. It's intended to be a very simple target just to verify that I3C
> is working on the guest. Internally, we've used it on Linux to verify
> that i3C devices can be probed and can send/receive data and send IBIs.
>
> The second target is a remote target. The intention of this is to be
> able to communicate to a target that exists outside of QEMU.
>
> Lastly we add hotplugging support. The hotplugging doesn't do anything too
> complicated, it just adds the device attempting to hotplug to the bus. It is
> the device's responsibility to hot-join and go through the DAA process to
> participate on the bus.
>
> Thanks!
> Joe
>
> Joe Komlodi (16):
> hw/misc/aspeed_i3c: Move to i3c directory
> hw/i3c: Add bus support
> hw/i3c/aspeed_i3c: Add more register fields
> hw/i3c/aspeed_i3c: Add more reset values
> hw/i3c/aspeed_i3c: Add register RO field masks
> hw/i3c/aspeed_i3c: Treat more registers as read-as-zero
> hw/i3c/aspeed_i3c: Use 32 bits on MMIO writes
> hw/i3c/aspeed_i3c: Add IRQ MMIO behavior
> hw/i3c/aspeed_i3c: Add data TX and RX
> hw/i3c/aspeed_i3c: Add IBI handling
> hw/i3c/aspeed_i3c: Add ctrl MMIO handling
> hw/i3c/aspeed_i3c: Add controller resets
> hw/i3c: Add Mock target
> hw/i3c: remote_i3c: Add model
> qtest: remote_i3c: Add remote I3C qtest
> hw/i3c: Add hotplug support
Isn't this the designware i3c ip block, and as such could we name
it so? I was going to send an i2c only version of this but it seems
you've beaten me to it and got the i3c core going.
> hw/Kconfig | 1 +
> hw/arm/Kconfig | 2 +
> hw/i3c/Kconfig | 17 +
> hw/i3c/aspeed_i3c.c | 2044 +++++++++++++++++++++++++++++++++
> hw/i3c/core.c | 646 +++++++++++
> hw/i3c/meson.build | 6 +
> hw/i3c/mock-target.c | 314 +++++
> hw/i3c/remote-i3c.c | 469 ++++++++
> hw/i3c/trace-events | 52 +
> hw/i3c/trace.h | 1 +
> hw/meson.build | 1 +
> hw/misc/aspeed_i3c.c | 384 -------
> hw/misc/meson.build | 1 -
> hw/misc/trace-events | 6 -
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/i3c/aspeed_i3c.h | 207 ++++
> include/hw/i3c/i3c.h | 275 +++++
> include/hw/i3c/mock-target.h | 60 +
> include/hw/i3c/remote-i3c.h | 72 ++
> include/hw/misc/aspeed_i3c.h | 48 -
> meson.build | 1 +
> tests/qtest/meson.build | 1 +
> tests/qtest/remote-i3c-test.c | 610 ++++++++++
> 23 files changed, 4780 insertions(+), 440 deletions(-)
> create mode 100644 hw/i3c/Kconfig
> create mode 100644 hw/i3c/aspeed_i3c.c
> create mode 100644 hw/i3c/core.c
> create mode 100644 hw/i3c/meson.build
> create mode 100644 hw/i3c/mock-target.c
> create mode 100644 hw/i3c/remote-i3c.c
> create mode 100644 hw/i3c/trace-events
> create mode 100644 hw/i3c/trace.h
> delete mode 100644 hw/misc/aspeed_i3c.c
> create mode 100644 include/hw/i3c/aspeed_i3c.h
> create mode 100644 include/hw/i3c/i3c.h
> create mode 100644 include/hw/i3c/mock-target.h
> create mode 100644 include/hw/i3c/remote-i3c.h
> delete mode 100644 include/hw/misc/aspeed_i3c.h
> create mode 100644 tests/qtest/remote-i3c-test.c
>
> --
> 2.40.0.348.gf938b09366-goog
>
>
--
Ben Dooks, ben@fluff.org, http://www.fluff.org/ben/
Large Hadron Colada: A large Pina Colada that makes the universe disappear.
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 00/16] i3c: aspeed: Add I3C support
2023-04-01 17:28 ` [PATCH 00/16] i3c: aspeed: Add I3C support Ben Dooks
@ 2023-04-02 7:33 ` Cédric Le Goater
2023-04-02 8:11 ` Jeremy Kerr
0 siblings, 1 reply; 30+ messages in thread
From: Cédric Le Goater @ 2023-04-02 7:33 UTC (permalink / raw)
To: Ben Dooks, Joe Komlodi
Cc: qemu-devel, venture, peter.maydell, Jeremy Kerr, Joel Stanley,
Andrew Jeffery, qemu-arm, Troy Lee, Graeme Gregory
Hello,
On 4/1/23 19:28, Ben Dooks wrote:
> On Fri, Mar 31, 2023 at 01:01:15AM +0000, Joe Komlodi wrote:
>> Hi all,
>>
>> This series adds I3C bus support to QEMU and adds more functionality to the
>> Aspeed I3C controller.
>>
>> This implementation is a basic implementation that introduces IBIs
>> (including hot-join), CCCs, and SDR data transfer. As-is, it doesnt support
>> multi-controller buses or HDR transfers.
>>
>> First we add the I3C bus and controller model. With that added we
>> gradually extend the functionality of the Aspeed I3C controller so it
>> can do transfers.
>>
>> With that added, we add 2 targets. The first target is a mock I3C
>> target. It's intended to be a very simple target just to verify that I3C
>> is working on the guest. Internally, we've used it on Linux to verify
>> that i3C devices can be probed and can send/receive data and send IBIs.
>>
>> The second target is a remote target. The intention of this is to be
>> able to communicate to a target that exists outside of QEMU.
>>
>> Lastly we add hotplugging support. The hotplugging doesn't do anything too
>> complicated, it just adds the device attempting to hotplug to the bus. It is
>> the device's responsibility to hot-join and go through the DAA process to
>> participate on the bus.
>>
>> Thanks!
>> Joe
>>
>> Joe Komlodi (16):
>> hw/misc/aspeed_i3c: Move to i3c directory
>> hw/i3c: Add bus support
>> hw/i3c/aspeed_i3c: Add more register fields
>> hw/i3c/aspeed_i3c: Add more reset values
>> hw/i3c/aspeed_i3c: Add register RO field masks
>> hw/i3c/aspeed_i3c: Treat more registers as read-as-zero
>> hw/i3c/aspeed_i3c: Use 32 bits on MMIO writes
>> hw/i3c/aspeed_i3c: Add IRQ MMIO behavior
>> hw/i3c/aspeed_i3c: Add data TX and RX
>> hw/i3c/aspeed_i3c: Add IBI handling
>> hw/i3c/aspeed_i3c: Add ctrl MMIO handling
>> hw/i3c/aspeed_i3c: Add controller resets
>> hw/i3c: Add Mock target
>> hw/i3c: remote_i3c: Add model
>> qtest: remote_i3c: Add remote I3C qtest
>> hw/i3c: Add hotplug support
>
> Isn't this the designware i3c ip block, and as such could we name
> it so?
Currently, QEMU only has a model for a dummy Aspeed I3C variant so this is a
great addition.
> I was going to send an i2c only version of this but it seems you've beaten me
> to it and got the i3c core going.
I gave the model a try adding a sensor on the legacy bus of an ast2600-evb
machine :
-device tmp105,bus=aspeed.i3c.device.1-legacy-i2c,address=0x4d,id=tmp-test
Looks good. Next step would be to add some real I3C device model.
According to recent work on the kernel, it is indeed based on designware I3C :
https://lore.kernel.org/all/20230331091501.3800299-1-jk@codeconstruct.com.au/
Jeremy, how different is it ? Could we introduce properties or sub classes,
to support both.
Thanks,
C.
>
>> hw/Kconfig | 1 +
>> hw/arm/Kconfig | 2 +
>> hw/i3c/Kconfig | 17 +
>> hw/i3c/aspeed_i3c.c | 2044 +++++++++++++++++++++++++++++++++
>> hw/i3c/core.c | 646 +++++++++++
>> hw/i3c/meson.build | 6 +
>> hw/i3c/mock-target.c | 314 +++++
>> hw/i3c/remote-i3c.c | 469 ++++++++
>> hw/i3c/trace-events | 52 +
>> hw/i3c/trace.h | 1 +
>> hw/meson.build | 1 +
>> hw/misc/aspeed_i3c.c | 384 -------
>> hw/misc/meson.build | 1 -
>> hw/misc/trace-events | 6 -
>> include/hw/arm/aspeed_soc.h | 2 +-
>> include/hw/i3c/aspeed_i3c.h | 207 ++++
>> include/hw/i3c/i3c.h | 275 +++++
>> include/hw/i3c/mock-target.h | 60 +
>> include/hw/i3c/remote-i3c.h | 72 ++
>> include/hw/misc/aspeed_i3c.h | 48 -
>> meson.build | 1 +
>> tests/qtest/meson.build | 1 +
>> tests/qtest/remote-i3c-test.c | 610 ++++++++++
>> 23 files changed, 4780 insertions(+), 440 deletions(-)
>> create mode 100644 hw/i3c/Kconfig
>> create mode 100644 hw/i3c/aspeed_i3c.c
>> create mode 100644 hw/i3c/core.c
>> create mode 100644 hw/i3c/meson.build
>> create mode 100644 hw/i3c/mock-target.c
>> create mode 100644 hw/i3c/remote-i3c.c
>> create mode 100644 hw/i3c/trace-events
>> create mode 100644 hw/i3c/trace.h
>> delete mode 100644 hw/misc/aspeed_i3c.c
>> create mode 100644 include/hw/i3c/aspeed_i3c.h
>> create mode 100644 include/hw/i3c/i3c.h
>> create mode 100644 include/hw/i3c/mock-target.h
>> create mode 100644 include/hw/i3c/remote-i3c.h
>> delete mode 100644 include/hw/misc/aspeed_i3c.h
>> create mode 100644 tests/qtest/remote-i3c-test.c
>>
>> --
>> 2.40.0.348.gf938b09366-goog
>>
>>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 00/16] i3c: aspeed: Add I3C support
2023-04-02 7:33 ` Cédric Le Goater
@ 2023-04-02 8:11 ` Jeremy Kerr
2023-04-05 1:55 ` Joe Komlodi
0 siblings, 1 reply; 30+ messages in thread
From: Jeremy Kerr @ 2023-04-02 8:11 UTC (permalink / raw)
To: Cédric Le Goater, Ben Dooks, Joe Komlodi
Cc: qemu-devel, venture, peter.maydell, Joel Stanley, Andrew Jeffery,
qemu-arm, Troy Lee, Graeme Gregory
Hi Cédric,
> > Isn't this the designware i3c ip block, and as such could we name
> > it so?
>
> Currently, QEMU only has a model for a dummy Aspeed I3C variant so
> this is a great addition.
[...]
> According to recent work on the kernel, it is indeed based on
> designware I3C :
>
> https://lore.kernel.org/all/20230331091501.3800299-1-jk@codeconstruct.com.au/
>
> Jeremy, how different is it ? Could we introduce properties or sub
> classes, to support both.
The differences (at least from the view of the current Linux driver
implementation) are very minor; unless we want to be errata-compatible,
you could use the dw driver directly, plus the ast2600-specific global
register space.
Cheers,
Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 00/16] i3c: aspeed: Add I3C support
2023-04-02 8:11 ` Jeremy Kerr
@ 2023-04-05 1:55 ` Joe Komlodi
2023-04-05 2:06 ` Jeremy Kerr
0 siblings, 1 reply; 30+ messages in thread
From: Joe Komlodi @ 2023-04-05 1:55 UTC (permalink / raw)
To: Jeremy Kerr
Cc: Cédric Le Goater, Ben Dooks, qemu-devel, venture,
peter.maydell, Joel Stanley, Andrew Jeffery, qemu-arm, Troy Lee,
Graeme Gregory
Hi all,
On Sun, Apr 2, 2023 at 1:11 AM Jeremy Kerr <jk@codeconstruct.com.au> wrote:
>
> Hi Cédric,
>
> > > Isn't this the designware i3c ip block, and as such could we name
> > > it so?
> >
> > Currently, QEMU only has a model for a dummy Aspeed I3C variant so
> > this is a great addition.
>
> [...]
>
> > According to recent work on the kernel, it is indeed based on
> > designware I3C :
> >
> > https://lore.kernel.org/all/20230331091501.3800299-1-jk@codeconstruct.com.au/
> >
> > Jeremy, how different is it ? Could we introduce properties or sub
> > classes, to support both.
>
> The differences (at least from the view of the current Linux driver
> implementation) are very minor; unless we want to be errata-compatible,
> you could use the dw driver directly, plus the ast2600-specific global
> register space.
>
This is my understanding as well from an outside look.
From a QEMU standpoint I could split off the dwc portion into a
dwc_i3c model, which the aspeed_i3c portion inherits from. I can do
that in a v2 if that sounds good with everyone.
Thanks,
Joe
> Cheers,
>
>
> Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 00/16] i3c: aspeed: Add I3C support
2023-04-05 1:55 ` Joe Komlodi
@ 2023-04-05 2:06 ` Jeremy Kerr
2023-04-05 2:30 ` Joel Stanley
0 siblings, 1 reply; 30+ messages in thread
From: Jeremy Kerr @ 2023-04-05 2:06 UTC (permalink / raw)
To: Joe Komlodi
Cc: Cédric Le Goater, Ben Dooks, qemu-devel, venture,
peter.maydell, Joel Stanley, Andrew Jeffery, qemu-arm, Troy Lee,
Graeme Gregory
Hi Joe,
> > > Jeremy, how different is it ? Could we introduce properties or sub
> > > classes, to support both.
> >
> > The differences (at least from the view of the current Linux driver
> > implementation) are very minor; unless we want to be errata-compatible,
> > you could use the dw driver directly, plus the ast2600-specific global
> > register space.
> >
>
> This is my understanding as well from an outside look.
> From a QEMU standpoint I could split off the dwc portion into a
> dwc_i3c model, which the aspeed_i3c portion inherits from. I can do
> that in a v2 if that sounds good with everyone.
I'm not a qemu maintainer, but for the record: I'm fine with the current
approach. I don't have access to any of the non-aspeed dw documentation,
so verifying what should go into the dw model vs. what is
ast2600-specific has been a bit tricky.
If someone needs a non-aspeed dw model, and has a bit of documentation
about the underlying dw hardware, it should be easy enough to split back
out. Maybe just make sure any "known" divergences - like the IBI PEC
behaviour - are well commented.
That said, if you're keen to do the split dw+aspeed models, that's also
good :)
Cheers,
Jeremy
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 00/16] i3c: aspeed: Add I3C support
2023-04-05 2:06 ` Jeremy Kerr
@ 2023-04-05 2:30 ` Joel Stanley
0 siblings, 0 replies; 30+ messages in thread
From: Joel Stanley @ 2023-04-05 2:30 UTC (permalink / raw)
To: Jeremy Kerr
Cc: Joe Komlodi, Cédric Le Goater, Ben Dooks, qemu-devel,
venture, peter.maydell, Andrew Jeffery, qemu-arm, Troy Lee,
Graeme Gregory
On Wed, 5 Apr 2023 at 02:07, Jeremy Kerr <jk@codeconstruct.com.au> wrote:
>
> Hi Joe,
>
> > > > Jeremy, how different is it ? Could we introduce properties or sub
> > > > classes, to support both.
> > >
> > > The differences (at least from the view of the current Linux driver
> > > implementation) are very minor; unless we want to be errata-compatible,
> > > you could use the dw driver directly, plus the ast2600-specific global
> > > register space.
> > >
> >
> > This is my understanding as well from an outside look.
> > From a QEMU standpoint I could split off the dwc portion into a
> > dwc_i3c model, which the aspeed_i3c portion inherits from. I can do
> > that in a v2 if that sounds good with everyone.
>
> I'm not a qemu maintainer, but for the record: I'm fine with the current
> approach. I don't have access to any of the non-aspeed dw documentation,
> so verifying what should go into the dw model vs. what is
> ast2600-specific has been a bit tricky.
>
> If someone needs a non-aspeed dw model, and has a bit of documentation
> about the underlying dw hardware, it should be easy enough to split back
> out. Maybe just make sure any "known" divergences - like the IBI PEC
> behaviour - are well commented.
>
> That said, if you're keen to do the split dw+aspeed models, that's also
> good :)
I think the split makes sense. It will help other platforms who have
the designware part add it to their system in the future.
Joe, when you send out the patches again please be sure to use
get_maintianers.pl to send it to the appropriate reviewers. Thanks for
sharing your work!
Cheers,
Joel
^ permalink raw reply [flat|nested] 30+ messages in thread