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From: weiwei <liweiwei@iscas.ac.cn>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: liweiwei@iscas.ac.cn, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
	lazyparser@gmail.com
Subject: Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Date: Tue, 14 Feb 2023 21:44:42 +0800	[thread overview]
Message-ID: <55b3b8c8-9f53-a46c-8bfc-a107164e0242@iscas.ac.cn> (raw)
In-Reply-To: <77307e37-6144-b8b3-ac6f-7ad3ae3aefa8@ventanamicro.com>


On 2023/2/14 21:37, Daniel Henrique Barboza wrote:
>
>
> On 2/14/23 05:38, Weiwei Li wrote:
>> Only V extension support EEW = 64 in these case: Zve64* extensions
>> don't support EEW = 64 as commented
>
> "as commented" where? In the previous patch?
>
>
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>
> The code LGTM.
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
>
>>   target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++--------
>>   1 file changed, 4 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
>> b/target/riscv/insn_trans/trans_rvv.c.inc
>> index 5dbdce073b..fc0d0d60e8 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * are not included for EEW=64 in Zve64*. (Section 18.2)
>>        */
".... are not included for EEW=64 in Zve64*. (Section 18.2) "

The comment is here, and similar comments can be found in following code.

Regards,

Weiwei Li

>>       return opivv_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
>> @@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * are not included for EEW=64 in Zve64*. (Section 18.2)
>>        */
>>       return opivx_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
>> @@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * for EEW=64 in Zve64*. (Section 18.2)
>>        */
>>       return opivv_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
>> @@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * for EEW=64 in Zve64*. (Section 18.2)
>>        */
>>       return opivx_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)



  reply	other threads:[~2023-02-14 14:08 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-14  8:38 [Patch 00/14] target/riscv: Some updates to float point related extensions Weiwei Li
2023-02-14  8:38 ` [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh Weiwei Li
2023-02-14 12:09   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx Weiwei Li
2023-02-14 12:10   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin Weiwei Li
2023-02-14 12:12   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 04/14] target/riscv: Add cfg properties for Zv* extension Weiwei Li
2023-02-14 12:14   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D Weiwei Li
2023-02-14 13:21   ` Daniel Henrique Barboza
2023-02-14 13:40     ` weiwei
2023-02-14 14:23       ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions Weiwei Li
2023-02-14 13:23   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 07/14] target/riscv: Indent fixes in cpu.c Weiwei Li
2023-02-14 13:24   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f Weiwei Li
2023-02-14 13:25   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc Weiwei Li
2023-02-14 13:26   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f Weiwei Li
2023-02-14 13:28   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions Weiwei Li
2023-02-14 13:30   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64 Weiwei Li
2023-02-14 13:33   ` Daniel Henrique Barboza
2023-02-14  8:38 ` [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc Weiwei Li
2023-02-14 13:37   ` Daniel Henrique Barboza
2023-02-14 13:44     ` weiwei [this message]
2023-02-14  8:38 ` [Patch 14/14] target/riscv: Expose properties for Zv* extension Weiwei Li
2023-02-14 13:39   ` Daniel Henrique Barboza

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